multiplier_8_bit.vhd

This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multip

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 

entity multiplier_8_bit is
	port
	(
		rst	: in std_logic;
		clk	  : in std_logic;

		A : in std_logic_vector(7 downto 0);
		B : in std_logic_vector(7 downto 0);		
		
		M  : out std_logic_vector(15 downto 0)	
	);
end multiplier_8_bit;

architecture Behavioral of multiplier_8_bit is
	signal regA,regB,regS,Sout,tmpA  : std_logic_vector(7 downto 0);
	signal C,Cout,add_shift : std_logic;


component RCA_8bit is                                                       
Port ( a, b : in std_logic_vector(7 downto 0);                           
       c : in std_logic;                                                  
       sum :  out std_logic_vector(7 downto 0);                             
       carry_out : out std_logic);                                       
end component;      



begin
	
M <= regS & regB;

add : RCA_8bit port map(regS, tmpA, '0', Sout, Cout);
tmpA <= regA when regB(0) = '1' else "00000000";
 	 
	 
	
  process(clk)
  begin
  	if clk'event and clk = '1' then
  		if rst = '1' then
  			regA<=A;
  			regB<=B;
  			regS<="00000000";
  			add_shift<='1';
  		elsif add_shift = '1' then
  			regS <= Sout;
  			C <= Cout;
  			add_shift <= '0';
  		else
  			regB <= regS(0) & regB(7 downto 1);
  			regS <= C & regS(7 downto 1);
  			add_shift <= '1';
  		end if;
  	end if;
  end process;
  
end Behavioral;
				
--	A	<= SXT(A(1 downto 7),8) + SXT((M(1 downto 7) and Q(7)&Q(7)&Q(7)&Q(7)&Q(7)&Q(7)&Q(7)),8); 
	
	                                
--	process(clk)
--		--variable var_COUNT	: std_logic_vecdowntor(0 downto 2);
--		variable temp_A	: std_logic;
--	--	variable temp_A	: std_logic_vecdowntor(0 downto 7);
--	begin
--		if clk'event and clk = '1' then			
--			if reset = '1' then
--				A	    <= "00000000";
--				COUNT	<= "000";
--				M <= din_A;
--				Q <= din_B;
--				shift <= '0';
--				finish <= '0';
--				done<='0';
--			
--			elsif shift = '0' then --and COUNT /= "111" then		
--				if Q(7) = '0' then
--					A <= '0' & A(7 downto 1); 
--				else
--					if M(7)='1' and A(7)='1' then
--						A <= '1' & A(7 downto 1)+ M(7 downto 1);
--					else
--						A <= '0' & A(7 downto 1)+ M(7 downto 1);
--					end if;
--				end if;		
--			  shift <= '1';
--			  temp_A := A(7);
--			  	
--			elsif shift = '1' then		
--				A     <= '0' & A(7 downto 1);
--				Q     <= temp_A  & Q(7 downto 1);
--			  shift <= '0';  
--			 	COUNT <= COUNT + '1';	 		
--
--			 	if COUNT = "111" then
--			 		--A(0) <=M(0) xor Q(7);
--					--Q(7) <= '0';
--					done <= '1';			 	
--			 	end if;
--			 	
--			 		
--			
--		  
--						
--						
----			elsif finish ='1' then 
----				Q(7)     <= '0';
----				finish   <= '0';
----				done     <= '1';
----					
----			elsif shift = '0' then 
----				temp_A := A(7) and M(7) and Q(7);
----				A(0 downto 6)<= A(1 downto 7) + (M(1 downto 7) and Q(7)&Q(7)&Q(7)&Q(7)&Q(7)&Q(7)&Q(7));
----				--temp_A := temp_A_msb & A(0 downto 6)	
----				--msb_A  <= temp_A;
----				shift <= '1';
----			elsif shift = '1' then				
----				--A <= '0' & A(0 downto 6);
----				--msb_A  <= temp_A;
----				A <= '0' & A(0 downto 6);
----				Q <= temp_A  & Q(0 downto 6);
----				--Q <= A(7) & Q(0 downto 6);				
----				COUNT <= COUNT + '1';	
----				shift <= '0';	
----				
----			elsif COUNT = "111" then
----				A(0)     <= M(0) xor Q(7);
----				finish   <='1';		
--				
--			
--				
--			end if;
--		end if;
--	end process;
--	
--	
--	
--end Behavioral;