prev_cmp_full_adder.map.qmsg

这是一个基于嵌入式的利用硬件高级描述语言编写的全加器程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 04 01:40:35 2008 " "Info: Processing started: Tue Nov 04 01:40:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "full_adder " "Warning: Ignored assignments for entity \"full_adder\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -section_id \"Root Region\" " "Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -section_id \"Root Region\" is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id \"Root Region\" " "Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id \"Root Region\" is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -section_id Top " "Warning: Assignment of entity set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/altera/jobs/full_adder.vhd " "Warning: Can't analyze file -- file C:/altera/jobs/full_adder.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "half_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file half_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 half_adder-half_adder " "Info: Found design unit 1: half_adder-half_adder" {  } { { "half_adder.vhd" "" { Text "C:/altera/jobs/half_adder.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 half_adder " "Info: Found entity 1: half_adder" {  } { { "half_adder.vhd" "" { Text "C:/altera/jobs/half_adder.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "full_adder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Info: Found entity 1: full_adder" {  } { { "full_adder.bdf" "" { Schematic "C:/altera/jobs/full_adder.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "full_adder " "Info: Elaborating entity \"full_adder\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "half_adder half_adder:inst " "Info: Elaborating entity \"half_adder\" for hierarchy \"half_adder:inst\"" {  } { { "full_adder.bdf" "inst" { Schematic "C:/altera/jobs/full_adder.bdf" { { 64 336 432 160 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Allocated 155 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 04 01:40:51 2008 " "Info: Processing ended: Tue Nov 04 01:40:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Info: Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}