cpu.cmp.logdb

用VHDL语言设计简单的CPU

v1
REGISTER_PACKING,REG_PACK_TYPE_FINISHED,ADATA,0,acc[15],acc[15],
RAM_PACKING,0,M4K,18,18,TrueDual,0,17,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[31],
RAM_PACKING,0,M4K,18,18,TrueDual,0,16,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[30],
RAM_PACKING,0,M4K,18,18,TrueDual,0,15,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[29],
RAM_PACKING,0,M4K,18,18,TrueDual,0,14,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[28],
RAM_PACKING,0,M4K,18,18,TrueDual,0,13,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[27],
RAM_PACKING,0,M4K,18,18,TrueDual,0,12,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[26],
RAM_PACKING,0,M4K,18,18,TrueDual,0,11,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[25],
RAM_PACKING,0,M4K,18,18,TrueDual,0,10,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[24],
RAM_PACKING,0,M4K,18,18,TrueDual,0,9,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[23],
RAM_PACKING,0,M4K,18,18,TrueDual,0,8,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[22],
RAM_PACKING,0,M4K,18,18,TrueDual,0,7,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[21],
RAM_PACKING,0,M4K,18,18,TrueDual,0,6,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[20],
RAM_PACKING,0,M4K,18,18,TrueDual,0,5,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[19],
RAM_PACKING,0,M4K,18,18,TrueDual,0,4,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[18],
RAM_PACKING,0,M4K,18,18,TrueDual,0,3,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[17],
RAM_PACKING,0,M4K,18,18,TrueDual,0,2,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[16],
RAM_PACKING,0,M4K,18,18,TrueDual,0,1,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[15],
RAM_PACKING,0,M4K,18,18,TrueDual,0,0,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[14],
RAM_PACKING,1,M4K,18,18,TrueDual,0,13,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[13],
RAM_PACKING,1,M4K,18,18,TrueDual,0,12,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[12],
RAM_PACKING,1,M4K,18,18,TrueDual,0,11,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[11],
RAM_PACKING,1,M4K,18,18,TrueDual,0,10,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[10],
RAM_PACKING,1,M4K,18,18,TrueDual,0,9,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[9],
RAM_PACKING,1,M4K,18,18,TrueDual,0,8,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[8],
RAM_PACKING,1,M4K,18,18,TrueDual,0,7,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[7],
RAM_PACKING,1,M4K,18,18,TrueDual,0,6,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[6],
RAM_PACKING,1,M4K,18,18,TrueDual,0,5,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[5],
RAM_PACKING,1,M4K,18,18,TrueDual,0,4,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[4],
RAM_PACKING,1,M4K,18,18,TrueDual,0,3,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[3],
RAM_PACKING,1,M4K,18,18,TrueDual,0,2,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[2],
RAM_PACKING,1,M4K,18,18,TrueDual,0,1,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[1],
RAM_PACKING,1,M4K,18,18,TrueDual,0,0,10000000,lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|q_a[0],
RAM_PACKING,2,M4K,18,18,TrueDual,0,15,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[15],
RAM_PACKING,2,M4K,18,18,TrueDual,0,14,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[14],
RAM_PACKING,2,M4K,18,18,TrueDual,0,13,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[13],
RAM_PACKING,2,M4K,18,18,TrueDual,0,12,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[12],
RAM_PACKING,2,M4K,18,18,TrueDual,0,11,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[11],
RAM_PACKING,2,M4K,18,18,TrueDual,0,10,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[10],
RAM_PACKING,2,M4K,18,18,TrueDual,0,9,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[9],
RAM_PACKING,2,M4K,18,18,TrueDual,0,8,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[8],
RAM_PACKING,2,M4K,18,18,TrueDual,0,7,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[7],
RAM_PACKING,2,M4K,18,18,TrueDual,0,6,10000010,lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[6],