prev_cmp_cpu.map.qmsg

用VHDL语言设计简单的CPU

{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0:inst8\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst8\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.vhd" "" { Text "F:/another way/cpu/lpm_rom0.vhd" 84 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_js61.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_js61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_js61 " "Info: Found entity 1: altsyncram_js61" {  } { { "db/altsyncram_js61.tdf" "" { Text "F:/another way/cpu/db/altsyncram_js61.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_js61 lpm_rom0:inst8\|altsyncram:altsyncram_component\|altsyncram_js61:auto_generated " "Info: Elaborating entity \"altsyncram_js61\" for hierarchy \"lpm_rom0:inst8\|altsyncram:altsyncram_component\|altsyncram_js61:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_unit control_unit:inst2 " "Info: Elaborating entity \"control_unit\" for hierarchy \"control_unit:inst2\"" {  } { { "cpu.bdf" "inst2" { Schematic "F:/another way/cpu/cpu.bdf" { { 240 416 608 368 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ir ir:inst4 " "Info: Elaborating entity \"ir\" for hierarchy \"ir:inst4\"" {  } { { "cpu.bdf" "inst4" { Schematic "F:/another way/cpu/cpu.bdf" { { 352 24 192 448 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mbr mbr:inst3 " "Info: Elaborating entity \"mbr\" for hierarchy \"mbr:inst3\"" {  } { { "cpu.bdf" "inst3" { Schematic "F:/another way/cpu/cpu.bdf" { { 208 24 240 336 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_ram_dq0.vhd 2 1 " "Warning: Using design file lpm_ram_dq0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_ram_dq0-SYN " "Info: Found design unit 1: lpm_ram_dq0-SYN" {  } { { "lpm_ram_dq0.vhd" "" { Text "F:/another way/cpu/lpm_ram_dq0.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dq0 " "Info: Found entity 1: lpm_ram_dq0" {  } { { "lpm_ram_dq0.vhd" "" { Text "F:/another way/cpu/lpm_ram_dq0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq0 lpm_ram_dq0:inst7 " "Info: Elaborating entity \"lpm_ram_dq0\" for hierarchy \"lpm_ram_dq0:inst7\"" {  } { { "cpu.bdf" "inst7" { Schematic "F:/another way/cpu/cpu.bdf" { { 464 24 184 576 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_ram_dq0:inst7\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\"" {  } { { "lpm_ram_dq0.vhd" "altsyncram_component" { Text "F:/another way/cpu/lpm_ram_dq0.vhd" 89 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_ram_dq0:inst7\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\"" {  } { { "lpm_ram_dq0.vhd" "" { Text "F:/another way/cpu/lpm_ram_dq0.vhd" 89 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3ac1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3ac1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3ac1 " "Info: Found entity 1: altsyncram_3ac1" {  } { { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_3ac1 lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated " "Info: Elaborating entity \"altsyncram_3ac1\" for hierarchy \"lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mar mar:inst6 " "Info: Elaborating entity \"mar\" for hierarchy \"mar:inst6\"" {  } { { "cpu.bdf" "inst6" { Schematic "F:/another way/cpu/cpu.bdf" { { 96 416 584 224 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pc pc:inst5 " "Info: Elaborating entity \"pc\" for hierarchy \"pc:inst5\"" {  } { { "cpu.bdf" "inst5" { Schematic "F:/another way/cpu/cpu.bdf" { { -16 416 592 80 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "pc:inst5\|pc_out\[2\] pc:inst5\|temp\[2\] " "Info: Duplicate register \"pc:inst5\|pc_out\[2\]\" merged to single register \"pc:inst5\|temp\[2\]\"" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pc:inst5\|pc_out\[1\] pc:inst5\|temp\[1\] " "Info: Duplicate register \"pc:inst5\|pc_out\[1\]\" merged to single register \"pc:inst5\|temp\[1\]\"" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pc:inst5\|pc_out\[0\] pc:inst5\|temp\[0\] " "Info: Duplicate register \"pc:inst5\|pc_out\[0\]\" merged to single register \"pc:inst5\|temp\[0\]\"" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pc:inst5\|temp\[7\] pc:inst5\|pc_out\[7\] " "Info: Duplicate register \"pc:inst5\|temp\[7\]\" merged to single register \"pc:inst5\|pc_out\[7\]\"" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pc:inst5\|temp\[6\] pc:inst5\|pc_out\[6\] " "Info: Duplicate register \"pc:inst5\|temp\[6\]\" merged to single register \"pc:inst5\|pc_out\[6\]\"" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pc:inst5\|temp\[5\] pc:inst5\|pc_out\[5\] " "Info: Duplicate register \"pc:inst5\|temp\[5\]\" merged to single register \"pc:inst5\|pc_out\[5\]\"" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pc:inst5\|temp\[4\] pc:inst5\|pc_out\[4\] " "Info: Duplicate register \"pc:inst5\|temp\[4\]\" merged to single register \"pc:inst5\|pc_out\[4\]\"" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "pc:inst5\|temp\[3\] pc:inst5\|pc_out\[3\] " "Info: Duplicate register \"pc:inst5\|temp\[3\]\" merged to single register \"pc:inst5\|pc_out\[3\]\"" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "339 " "Info: Implemented 339 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "128 " "Info: Implemented 128 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "162 " "Info: Implemented 162 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "48 " "Info: Implemented 48 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "172 " "Info: Allocated 172 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 29 14:19:21 2009 " "Info: Processing ended: Sun Mar 29 14:19:21 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}