prev_cmp_cpu.map.qmsg

用VHDL语言设计简单的CPU

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 29 14:19:17 2009 " "Info: Processing started: Sun Mar 29 14:19:17 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "br.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file br.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 br-behave " "Info: Found design unit 1: br-behave" {  } { { "br.vhd" "" { Text "F:/another way/cpu/br.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 br " "Info: Found entity 1: br" {  } { { "br.vhd" "" { Text "F:/another way/cpu/br.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file alu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alu-behave " "Info: Found design unit 1: alu-behave" {  } { { "alu.vhd" "" { Text "F:/another way/cpu/alu.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 alu " "Info: Found entity 1: alu" {  } { { "alu.vhd" "" { Text "F:/another way/cpu/alu.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mbr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mbr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mbr-behave " "Info: Found design unit 1: mbr-behave" {  } { { "mbr.vhd" "" { Text "F:/another way/cpu/mbr.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 mbr " "Info: Found entity 1: mbr" {  } { { "mbr.vhd" "" { Text "F:/another way/cpu/mbr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ir.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ir.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ir-behave " "Info: Found design unit 1: ir-behave" {  } { { "ir.vhd" "" { Text "F:/another way/cpu/ir.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ir " "Info: Found entity 1: ir" {  } { { "ir.vhd" "" { Text "F:/another way/cpu/ir.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pc.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pc-behave " "Info: Found design unit 1: pc-behave" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pc " "Info: Found entity 1: pc" {  } { { "pc.vhd" "" { Text "F:/another way/cpu/pc.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mar.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mar.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mar-behave " "Info: Found design unit 1: mar-behave" {  } { { "mar.vhd" "" { Text "F:/another way/cpu/mar.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 mar " "Info: Found entity 1: mar" {  } { { "mar.vhd" "" { Text "F:/another way/cpu/mar.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control_unit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file control_unit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 control_unit-behave " "Info: Found design unit 1: control_unit-behave" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 control_unit " "Info: Found entity 1: control_unit" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file cpu.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Info: Found entity 1: cpu" {  } { { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cpu " "Info: Elaborating entity \"cpu\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu alu:inst " "Info: Elaborating entity \"alu\" for hierarchy \"alu:inst\"" {  } { { "cpu.bdf" "inst" { Schematic "F:/another way/cpu/cpu.bdf" { { 96 24 184 192 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "br br:inst1 " "Info: Elaborating entity \"br\" for hierarchy \"br:inst1\"" {  } { { "cpu.bdf" "inst1" { Schematic "F:/another way/cpu/cpu.bdf" { { -16 24 208 80 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom0.vhd 2 1 " "Warning: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom0-SYN " "Info: Found design unit 1: lpm_rom0-SYN" {  } { { "lpm_rom0.vhd" "" { Text "F:/another way/cpu/lpm_rom0.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.vhd" "" { Text "F:/another way/cpu/lpm_rom0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:inst8 " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:inst8\"" {  } { { "cpu.bdf" "inst8" { Schematic "F:/another way/cpu/cpu.bdf" { { 240 736 896 320 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:inst8\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:inst8\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.vhd" "altsyncram_component" { Text "F:/another way/cpu/lpm_rom0.vhd" 84 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}