mar.vhd

用VHDL语言设计简单的CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mar is
	port
	(	pc,mbr:in std_logic_vector(7 downto 0);
		cs:in std_logic_vector(31 downto 0);
		clk:in std_logic;
		mar_out:out std_logic_vector(7 downto 0)
	);
end mar;

architecture behave of mar is 
begin
	process(clk)
		begin
			if clk'event and clk='1'then
				if cs(12)='1'then
					mar_out<=pc;
				elsif cs(13)='1'then
					mar_out<=mbr;
				end if;
			end if;
	end process;
end behave;