control_unit.vhd

来自「用VHDL语言设计简单的CPU」· VHDL 代码 · 共 60 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity control_unit is
	port 
	(	clk:in std_logic;
		flag:in std_logic;
		cs:in std_logic_vector(31 downto 0);
		ir_out:in std_logic_vector(7 downto 0);
		address_out:out std_logic_vector(7 downto 0)
	);
end control_unit;

architecture behave of control_unit is
begin
	process(clk)
		variable address:std_logic_vector(7 downto 0);
		begin
			if clk'event and clk='1' then
				if cs(4)='1'then 
					address:=address+1;--increment car
				elsif cs(5)='1'then
					address:="00000000";--reset car
				elsif cs(6)='1'then--load
					case ir_out is
						when "00000001"=>
							address:="00010000";--store
						when "00000010"=>
							address:="00010100";--load
						when "00000011"=>
							address:="00011001";--add
						when "00000100"=>
							address:="00011110";--sub
						when "00001010"=>
							address:="00000110";--and
		                when "00001011"=>
							address:="00001000";--or
						when "00001100"=>
							address:="00111001";--not
						when "00001101"=>
							address:="00111110";--shiftr
						when "00001110"=>
							address:="01000100";--shifrl
						when "00001000"=>
							address:="00101001";--mpy
						when "00000101"=>--jmpegz
							if flag='0'then
								address:="00100011";
							else address:="00100101";
							end if;
						when "00000111"=>
							address:="00100111";--halt
						when others=>null;
					end case;
					address_out<=address;
				end if;
			end if;
	end process;
end behave;