cpu.map.summary

用VHDL语言设计简单的CPU

Analysis & Synthesis Status : Successful - Sun Mar 29 14:56:21 2009
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
Revision Name : cpu
Top-level Entity Name : cpu
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 90
    Dedicated logic registers : 104
Total registers : 104
Total pins : 130
Total virtual pins : 0
Total block memory bits : 12,288
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0