ir.vhd

来自「用VHDL语言设计简单的CPU」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ir is
	port
	(	mbr_in:in std_logic_vector(7 downto 0);--mbr[15..8]
		cs:in std_logic_vector(31 downto 0);
		clk:in std_logic;
		ir_out:out std_logic_vector(7 downto 0)
	);
end ir;

architecture behave of ir is
begin
	process(clk)
		begin
			if clk'event and clk='1'then 
				if cs(7)='1'then
					ir_out<=mbr_in;
				end if;
			end if;
	end process;
end behave;