br.vhd

用VHDL语言设计简单的CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity br is
	port
	(	mbr_in:in std_logic_vector(15 downto 0);
		cs:in std_logic_vector(31 downto 0);
		clk:in std_logic;
		br_out:out std_logic_vector(15 downto 0)
	);
end br;

architecture behave of br is
begin
	process(clk)
		begin
			if clk'event and clk='1'then
				if cs(21)='1'then
					br_out<=mbr_in;
				end if;
			end if;
	end process;
end behave;