cpu.fit.summary

来自「用VHDL语言设计简单的CPU」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Sun Mar 29 14:56:34 2009
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
Revision Name : cpu
Top-level Entity Name : cpu
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : 1 %
    Combinational ALUTs : 91 / 12,480 ( < 1 % )
    Dedicated logic registers : 104 / 12,480 ( < 1 % )
Total registers : 104
Total pins : 130 / 343 ( 38 % )
Total virtual pins : 0
Total block memory bits : 12,288 / 419,328 ( 3 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )