cpu.fit.rpt

用VHDL语言设计简单的CPU

Fitter report for cpu
Sun Mar 29 14:56:35 2009
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Netlist Optimizations
  5. HardCopy II Device Resource Guide
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. Output Pin Default Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Delay Chain Summary
 15. Pad To Core Delay Chain Fanout
 16. Control Signals
 17. Global & Other Fast Signals
 18. Non-Global High Fan-Out Signals
 19. Fitter RAM Summary
 20. Interconnect Usage Summary
 21. LAB Logic Elements
 22. LAB-wide Signals
 23. LAB Signals Sourced
 24. LAB Signals Sourced Out
 25. LAB Distinct Inputs
 26. I/O Rules Summary
 27. I/O Rules Details
 28. I/O Rules Matrix
 29. Fitter Device Options
 30. Operating Settings and Conditions
 31. Advanced Data - General
 32. Advanced Data - Placement Preparation
 33. Advanced Data - Placement
 34. Advanced Data - Routing
 35. Fitter Messages
 36. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Fitter Summary                                                                ;
+-------------------------------+-----------------------------------------------+
; Fitter Status                 ; Successful - Sun Mar 29 14:56:34 2009         ;
; Quartus II Version            ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;
; Revision Name                 ; cpu                                           ;
; Top-level Entity Name         ; cpu                                           ;
; Family                        ; Stratix II                                    ;
; Device                        ; EP2S15F484C3                                  ;
; Timing Models                 ; Final                                         ;
; Logic utilization             ; 1 %                                           ;
;     Combinational ALUTs       ; 91 / 12,480 ( < 1 % )                         ;
;     Dedicated logic registers ; 104 / 12,480 ( < 1 % )                        ;
; Total registers               ; 104                                           ;