original_signal.tan.qmsg

来自「一种基于LUT的预失真方法。其中的一部分」· QMSG 代码 · 共 13 行 · 第 1/5 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clkin dataout\[15\] mod:inst4\|rfout\[18\] 5.243 ns register " "Info: tco from clock \"clkin\" to destination pin \"dataout\[15\]\" through register \"mod:inst4\|rfout\[18\]\" is 5.243 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clkin altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] -3.874 ns + " "Info: + Offset between input clock \"clkin\" and output clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" is -3.874 ns" {  } { { "original_signal.bdf" "" { Schematic "E:/Graduation_Design/Quartus/original_signal/original_signal.bdf" { { -16 8 176 0 "clkin" "" } } } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] source 4.321 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" to source register is 4.321 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.393 ns) + CELL(0.000 ns) 2.393 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl 2 COMB CLKCTRL_G3 579 " "Info: 2: + IC(2.393 ns) + CELL(0.000 ns) = 2.393 ns; Loc. = CLKCTRL_G3; Fanout = 579; COMB Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.690 ns) 4.321 ns mod:inst4\|rfout\[18\] 3 REG FF_X43_Y11_N19 1 " "Info: 3: + IC(1.238 ns) + CELL(0.690 ns) = 4.321 ns; Loc. = FF_X43_Y11_N19; Fanout = 1; REG Node = 'mod:inst4\|rfout\[18\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.928 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl mod:inst4|rfout[18] } "NODE_NAME" } } { "mod.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/mod.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.690 ns ( 15.97 % ) " "Info: Total cell delay = 0.690 ns ( 15.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.631 ns ( 84.03 % ) " "Info: Total interconnect delay = 3.631 ns ( 84.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.321 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl mod:inst4|rfout[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.321 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl mod:inst4|rfout[18] } { 0.000ns 2.393ns 1.238ns } { 0.000ns 0.000ns 0.690ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.279 ns + " "Info: + Micro clock to output delay of source is 0.279 ns" {  } { { "mod.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/mod.v" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.517 ns + Longest register pin " "Info: + Longest register to pin delay is 4.517 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mod:inst4\|rfout\[18\] 1 REG FF_X43_Y11_N19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X43_Y11_N19; Fanout = 1; REG Node = 'mod:inst4\|rfout\[18\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { mod:inst4|rfout[18] } "NODE_NAME" } } { "mod.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/mod.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.935 ns) + CELL(2.582 ns) 4.517 ns dataout\[15\]~output 2 COMB IOOBUF_X53_Y16_N8 1 " "Info: 2: + IC(1.935 ns) + CELL(2.582 ns) = 4.517 ns; Loc. = IOOBUF_X53_Y16_N8; Fanout = 1; COMB Node = 'dataout\[15\]~output'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.517 ns" { mod:inst4|rfout[18] dataout[15]~output