original_signal.tan.qmsg

来自「一种基于LUT的预失真方法。其中的一部分」· QMSG 代码 · 共 13 行 · 第 1/5 页

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] memory FIRInterp:inst8\|altsyncram:mem_rtl_0\|altsyncram_csi1:auto_generated\|ram_block1a0~portb_address_reg3 register FIRInterp:inst8\|Md\[9\] 6.26 ns " "Info: Slack time is 6.26 ns for clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" between source memory \"FIRInterp:inst8\|altsyncram:mem_rtl_0\|altsyncram_csi1:auto_generated\|ram_block1a0~portb_address_reg3\" and destination register \"FIRInterp:inst8\|Md\[9\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "111.19 MHz 8.994 ns " "Info: Fmax is 111.19 MHz (period= 8.994 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "14.208 ns + Largest memory register " "Info: + Largest memory to register requirement is 14.208 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "15.254 ns + " "Info: + Setup relationship between source and destination is 15.254 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 11.380 ns " "Info: + Latch edge is 11.380 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 15.254 ns -3.874 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" is 15.254 ns with  offset of -3.874 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -3.874 ns " "Info: - Launch edge is -3.874 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 15.254 ns -3.874 ns  50 " "Info: Clock period of Source clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" is 15.254 ns with  offset of -3.874 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.519 ns + Largest " "Info: + Largest clock skew is -0.519 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] destination 7.310 ns + Shortest register " "Info: + Shortest clock path from clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" to destination register is 7.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.393 ns) + CELL(0.000 ns) 2.393 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl 2 COMB CLKCTRL_G3 579 " "Info: 2: + IC(2.393 ns) + CELL(0.000 ns) = 2.393 ns; Loc. = CLKCTRL_G3; Fanout = 579; COMB Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.969 ns) 4.597 ns CLK_ALL_GEN:inst5\|count\[0\] 3 REG FF_X28_Y4_N19 4 " "Info: 3: + IC(1.235 ns) + CELL(0.969 ns) = 4.597 ns; Loc. = FF_X28_Y4_N19; Fanout = 4; REG Node = 'CLK_ALL_GEN:inst5\|count\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.204 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.883 ns) + CELL(0.000 ns) 5.480 ns CLK_ALL_GEN:inst5\|count\[0\]~clkctrl 4 COMB CLKCTRL_G15 255 " "Info: 4: + IC(0.883 ns) + CELL(0.000 ns) = 5.480 ns; Loc. = CLKCTRL_G15; Fanout = 255; COMB Node = 'CLK_ALL_GEN:inst5\|count\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.883 ns" { CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.229 ns) + CELL(0.601 ns) 7.310 ns FIRInterp:inst8\|Md\[9\] 5 REG DSPMULT_X42_Y13_N0 25 " "Info: 5: + IC(1.229 ns) + CELL(0.601 ns) = 7.310 ns; Loc. = DSPMULT_X42_Y13_N0; Fanout = 25; REG Node = 'FIRInterp:inst8\|Md\[9\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.830 ns" { CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|Md[9] } "NODE_NAME" } } { "FIR/FIRInterp.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.570 ns ( 21.48 % ) " "Info: Total cell delay = 1.570 ns ( 21.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.740 ns ( 78.52 % ) " "Info: Total interconnect delay = 5.740 ns ( 78.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.310 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|Md[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.310 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|Md[9] } { 0.000ns 2.393ns 1.235ns 0.883ns 1.229ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.601ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] source 7.829 ns - Longest memory " "Info: - Longest clock path from clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" to source memory is 7.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.393 ns) + CELL(0.000 ns) 2.393 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl 2 COMB CLKCTRL_G3 579 " "Info: 2: + IC(2.393 ns) + CELL(0.000 ns) = 2.393 ns; Loc. = CLKCTRL_G3; Fanout = 579; COMB Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.969 ns) 4.597 ns CLK_ALL_GEN:inst5\|count\[0\] 3 REG FF_X28_Y4_N19 4 " "Info: 3: + IC(1.235 ns) + CELL(0.969 ns) = 4.597 ns; Loc. = FF_X28_Y4_N19; Fanout = 4; REG Node = 'CLK_ALL_GEN:inst5\|count\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.204 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.883 ns) + CELL(0.000 ns) 5.480 ns CLK_ALL_GEN:inst5\|count\[0\]~clkctrl 4 COMB CLKCTRL_G15 255 " "Info: 4: + IC(0.883 ns) + CELL(0.000 ns) = 5.480 ns; Loc. = CLKCTRL_G15; Fanout = 255; COMB Node = 'CLK_ALL_GEN:inst5\|count\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.883 ns" { CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.229 ns) + CELL(1.120 ns) 7.829 ns FIRInterp:inst8\|altsyncram:mem_rtl_0\|altsyncram_csi1:auto_generated\|ram_block1a0~portb_address_reg3 5 MEM M9K_X33_Y12_N0 32 " "Info: 5: + IC(1.229 ns) + CELL(1.120 ns) = 7.829 ns; Loc. = M9K_X33_Y12_N0; Fanout = 32; MEM Node = 'FIRInterp:inst8\|altsyncram:mem_rtl_0\|altsyncram_csi1:auto_generated\|ram_block1a0~portb_address_reg3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "db/altsyncram_csi1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altsyncram_csi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.089 ns ( 26.68 % ) " "Info: Total cell delay = 2.089 ns ( 26.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.740 ns ( 73.32 % ) " "Info: Total interconnect delay = 5.740 ns ( 73.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.829 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.829 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } { 0.000ns 2.393ns 1.235ns 0.883ns 1.229ns } { 0.000ns 0.000ns 0.969ns 0.000ns 1.120ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.310 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|Md[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.310 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|Md[9] } { 0.000ns 2.393ns 1.235ns 0.883ns 1.229ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.601ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.829 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.829 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } { 0.000ns 2.393ns 1.235ns 0.883ns 1.229ns } { 0.000ns 0.000ns 0.969ns 0.000ns 1.120ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.297 ns - " "Info: - Micro clock to output delay of source is 0.297 ns" {  } { { "db/altsyncram_csi1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altsyncram_csi1.tdf" 46 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.230 ns - " "Info: - Micro setup delay of destination is 0.230 ns" {  } { { "FIR/FIRInterp.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 75 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.310 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|Md[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.310 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|Md[9] } { 0.000ns 2.393ns 1.235ns 0.883ns 1.229ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.601ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.829 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.829 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } { 0.000ns 2.393ns 1.235ns 0.883ns 1.229ns } { 0.000ns 0.000ns 0.969ns 0.000ns 1.120ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.948 ns - Longest memory register " "Info: - Longest memory to register delay is 7.948 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FIRInterp:inst8\|altsyncram:mem_rtl_0\|altsyncram_csi1:auto_generated\|ram_block1a0~portb_address_reg3 1 MEM M9K_X33_Y12_N0 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X33_Y12_N0; Fanout = 32; MEM Node = 'FIRInterp:inst8\|altsyncram:mem_rtl_0\|altsyncram_csi1:auto_generated\|ram_block1a0~portb_address_reg3'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "db/altsyncram_csi1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altsyncram_csi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.676 ns) 3.676 ns FIRInterp:inst8\|altsyncram:mem_rtl_0\|altsyncram_csi1:auto_generated\|q_b\[25\] 2 MEM M9K_X33_Y12_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(3.676 ns) = 3.676 ns; Loc. = M9K_X33_Y12_N0; Fanout = 1; MEM Node = 'FIRInterp:inst8\|altsyncram:mem_rtl_0\|altsyncram_csi1:auto_generated\|q_b\[25\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.676 ns" { FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|q_b[25] } "NODE_NAME" } } { "db/altsyncram_csi1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altsyncram_csi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.889 ns) + CELL(0.494 ns) 6.059 ns FIRInterp:inst8\|Md~201 3 COMB LCCOMB_X41_Y15_N4 1 " "Info: 3: + IC(1.889 ns) + CELL(0.494 ns) = 6.059 ns; Loc. = LCCOMB_X41_Y15_N4; Fanout = 1; COMB Node = 'FIRInterp:inst8\|Md~201'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.383 ns" { FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|q_b[25] FIRInterp:inst8|Md~201 } "NODE_NAME" } } { "FIR/FIRInterp.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.615 ns) + CELL(0.274 ns) 7.948 ns FIRInterp:inst8\|Md\[9\] 4 REG DSPMULT_X42_Y13_N0 25 " "Info: 4: + IC(1.615 ns) + CELL(0.274 ns) = 7.948 ns; Loc. = DSPMULT_X42_Y13_N0; Fanout = 25; REG Node = 'FIRInterp:inst8\|Md\[9\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.889 ns" { FIRInterp:inst8|Md~201 FIRInterp:inst8|Md[9] } "NODE_NAME" } } { "FIR/FIRInterp.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.444 ns ( 55.91 % ) " "Info: Total cell delay = 4.444 ns ( 55.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.504 ns ( 44.09 % ) " "Info: Total interconnect delay = 3.504 ns ( 44.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.948 ns" { FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|q_b[25] FIRInterp:inst8|Md~201 FIRInterp:inst8|Md[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.948 ns" { FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|q_b[25] FIRInterp:inst8|Md~201 FIRInterp:inst8|Md[9] } { 0.000ns 0.000ns 1.889ns 1.615ns } { 0.000ns 3.676ns 0.494ns 0.274ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.310 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|Md[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.310 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|Md[9] } { 0.000ns 2.393ns 1.235ns 0.883ns 1.229ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.601ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.829 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.829 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 } { 0.000ns 2.393ns 1.235ns 0.883ns 1.229ns } { 0.000ns 0.000ns 0.969ns 0.000ns 1.120ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.948 ns" { FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|q_b[25] FIRInterp:inst8|Md~201 FIRInterp:inst8|Md[9] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.948 ns" { FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3 FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|q_b[25] FIRInterp:inst8|Md~201 FIRInterp:inst8|Md[9] } { 0.000ns 0.000ns 1.889ns 1.615ns } { 0.000ns 3.676ns 0.494ns 0.274ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clkin " "Info: No valid register-to-register data paths exist for clock \"clkin\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}