original_signal.tan.qmsg

来自「一种基于LUT的预失真方法。其中的一部分」· QMSG 代码 · 共 13 行 · 第 1/5 页

{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0}
{ "Warning" "WTAN_PLL_CONFLICTING_GLOBAL_FMAX" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 65.56 MHz 140.02 MHz " "Warning: ClockLock PLL \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" input frequency requirement of 65.56 MHz overrides default required fmax of 140.02 MHz -- Slack information will be reported" {  } {  } 0 0 "ClockLock PLL \"%1!s!\" input frequency requirement of %2!s! overrides default required fmax of %3!s! -- Slack information will be reported" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_ALL_GEN:inst5\|count\[4\] " "Info: Detected ripple clock \"CLK_ALL_GEN:inst5\|count\[4\]\" as buffer" {  } { { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_ALL_GEN:inst5\|count\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_ALL_GEN:inst5\|count\[0\] " "Info: Detected ripple clock \"CLK_ALL_GEN:inst5\|count\[0\]\" as buffer" {  } { { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_ALL_GEN:inst5\|count\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}