original_signal.tan.qmsg

来自「一种基于LUT的预失真方法。其中的一部分」· QMSG 代码 · 共 13 行 · 第 1/5 页

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] register CLK_ALL_GEN:inst5\|count\[4\] register FIRInterp:inst8\|we -2.079 ns " "Info: Minimum slack time is -2.079 ns for clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" between source register \"CLK_ALL_GEN:inst5\|count\[4\]\" and destination register \"FIRInterp:inst8\|we\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.946 ns + Shortest register register " "Info: + Shortest register to register delay is 0.946 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_ALL_GEN:inst5\|count\[4\] 1 REG FF_X28_Y4_N31 44 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X28_Y4_N31; Fanout = 44; REG Node = 'CLK_ALL_GEN:inst5\|count\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_ALL_GEN:inst5|count[4] } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.468 ns) + CELL(0.478 ns) 0.946 ns FIRInterp:inst8\|we 2 REG FF_X28_Y4_N9 1 " "Info: 2: + IC(0.468 ns) + CELL(0.478 ns) = 0.946 ns; Loc. = FF_X28_Y4_N9; Fanout = 1; REG Node = 'FIRInterp:inst8\|we'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.946 ns" { CLK_ALL_GEN:inst5|count[4] FIRInterp:inst8|we } "NODE_NAME" } } { "FIR/FIRInterp.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 50.53 % ) " "Info: Total cell delay = 0.478 ns ( 50.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.468 ns ( 49.47 % ) " "Info: Total interconnect delay = 0.468 ns ( 49.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.946 ns" { CLK_ALL_GEN:inst5|count[4] FIRInterp:inst8|we } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.946 ns" { CLK_ALL_GEN:inst5|count[4] FIRInterp:inst8|we } { 0.000ns 0.468ns } { 0.000ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "3.025 ns - Smallest register register " "Info: - Smallest register to register requirement is 3.025 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -3.874 ns " "Info: + Latch edge is -3.874 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 15.254 ns -3.874 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" is 15.254 ns with  offset of -3.874 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -3.874 ns " "Info: - Launch edge is -3.874 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 15.254 ns -3.874 ns  50 " "Info: Clock period of Source clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" is 15.254 ns with  offset of -3.874 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.076 ns + Smallest " "Info: + Smallest clock skew is 3.076 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] destination 7.394 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" to destination register is 7.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.393 ns) + CELL(0.000 ns) 2.393 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl 2 COMB CLKCTRL_G3 579 " "Info: 2: + IC(2.393 ns) + CELL(0.000 ns) = 2.393 ns; Loc. = CLKCTRL_G3; Fanout = 579; COMB Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.969 ns) 4.597 ns CLK_ALL_GEN:inst5\|count\[0\] 3 REG FF_X28_Y4_N19 4 " "Info: 3: + IC(1.235 ns) + CELL(0.969 ns) = 4.597 ns; Loc. = FF_X28_Y4_N19; Fanout = 4; REG Node = 'CLK_ALL_GEN:inst5\|count\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.204 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.883 ns) + CELL(0.000 ns) 5.480 ns CLK_ALL_GEN:inst5\|count\[0\]~clkctrl 4 COMB CLKCTRL_G15 255 " "Info: 4: + IC(0.883 ns) + CELL(0.000 ns) = 5.480 ns; Loc. = CLKCTRL_G15; Fanout = 255; COMB Node = 'CLK_ALL_GEN:inst5\|count\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.883 ns" { CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.224 ns) + CELL(0.690 ns) 7.394 ns FIRInterp:inst8\|we 5 REG FF_X28_Y4_N9 1 " "Info: 5: + IC(1.224 ns) + CELL(0.690 ns) = 7.394 ns; Loc. = FF_X28_Y4_N9; Fanout = 1; REG Node = 'FIRInterp:inst8\|we'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.914 ns" { CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|we } "NODE_NAME" } } { "FIR/FIRInterp.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.659 ns ( 22.44 % ) " "Info: Total cell delay = 1.659 ns ( 22.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.735 ns ( 77.56 % ) " "Info: Total interconnect delay = 5.735 ns ( 77.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.394 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|we } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.394 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|we } { 0.000ns 2.393ns 1.235ns 0.883ns 1.224ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.690ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] source 4.318 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" to source register is 4.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.393 ns) + CELL(0.000 ns) 2.393 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl 2 COMB CLKCTRL_G3 579 " "Info: 2: + IC(2.393 ns) + CELL(0.000 ns) = 2.393 ns; Loc. = CLKCTRL_G3; Fanout = 579; COMB Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.690 ns) 4.318 ns CLK_ALL_GEN:inst5\|count\[4\] 3 REG FF_X28_Y4_N31 44 " "Info: 3: + IC(1.235 ns) + CELL(0.690 ns) = 4.318 ns; Loc. = FF_X28_Y4_N31; Fanout = 44; REG Node = 'CLK_ALL_GEN:inst5\|count\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.925 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.690 ns ( 15.98 % ) " "Info: Total cell delay = 0.690 ns ( 15.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.628 ns ( 84.02 % ) " "Info: Total interconnect delay = 3.628 ns ( 84.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.318 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.318 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } { 0.000ns 2.393ns 1.235ns } { 0.000ns 0.000ns 0.690ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.394 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|we } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.394 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|we } { 0.000ns 2.393ns 1.235ns 0.883ns 1.224ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.690ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.318 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.318 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } { 0.000ns 2.393ns 1.235ns } { 0.000ns 0.000ns 0.690ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.279 ns - " "Info: - Micro clock to output delay of source is 0.279 ns" {  } { { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.228 ns + " "Info: + Micro hold delay of destination is 0.228 ns" {  } { { "FIR/FIRInterp.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.394 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|we } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.394 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|we } { 0.000ns 2.393ns 1.235ns 0.883ns 1.224ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.690ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.318 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.318 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } { 0.000ns 2.393ns 1.235ns } { 0.000ns 0.000ns 0.690ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.946 ns" { CLK_ALL_GEN:inst5|count[4] FIRInterp:inst8|we } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.946 ns" { CLK_ALL_GEN:inst5|count[4] FIRInterp:inst8|we } { 0.000ns 0.468ns } { 0.000ns 0.478ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.394 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|we } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.394 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[0] CLK_ALL_GEN:inst5|count[0]~clkctrl FIRInterp:inst8|we } { 0.000ns 2.393ns 1.235ns 0.883ns 1.224ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.690ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.318 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.318 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } { 0.000ns 2.393ns 1.235ns } { 0.000ns 0.000ns 0.690ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 21 " "Warning: Can't achieve minimum setup and hold requirement altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] along 21 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "mod:inst4\|rposition\[17\] RstN clkin 6.731 ns register " "Info: tsu for register \"mod:inst4\|rposition\[17\]\" (data pin = \"RstN\", clock pin = \"clkin\") is 6.731 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.204 ns + Longest pin register " "Info: + Longest pin to register delay is 7.204 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RstN 1 PIN PIN_218 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_218; Fanout = 1; PIN Node = 'RstN'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RstN } "NODE_NAME" } } { "original_signal.bdf" "" { Schematic "E:/Graduation_Design/Quartus/original_signal/original_signal.bdf" { { 176 48 216 192 "RstN" "" } { 168 216 296 184 "RstN" "" } { 416 890 920 432 "RstN" "" } { 584 104 160 600 "RstN" "" } { 72 -80 -40 88 "RstN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.921 ns) 0.921 ns RstN~input 2 COMB IOIBUF_X20_Y34_N7 56 " "Info: 2: + IC(0.000 ns) + CELL(0.921 ns) = 0.921 ns; Loc. = IOIBUF_X20_Y34_N7; Fanout = 56; COMB Node = 'RstN~input'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.921 ns" { RstN RstN~input } "NODE_NAME" } } { "original_signal.bdf" "" { Schematic "E:/Graduation_Design/Quartus/original_signal/original_signal.bdf" { { 176 48 216 192 "RstN" "" } { 168 216 296 184 "RstN" "" } { 416 890 920 432 "RstN" "" } { 584 104 160 600 "RstN" "" } { 72 -80 -40 88 "RstN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.474 ns) + CELL(0.809 ns) 7.204 ns mod:inst4\|rposition\[17\] 3 REG FF_X43_Y11_N31 3 " "Info: 3: + IC(5.474 ns) + CELL(0.809 ns) = 7.204 ns; Loc. = FF_X43_Y11_N31; Fanout = 3; REG Node = 'mod:inst4\|rposition\[17\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.283 ns" { RstN~input mod:inst4|rposition[17] } "NODE_NAME" } } { "mod.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/mod.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.730 ns ( 24.01 % ) " "Info: Total cell delay = 1.730 ns ( 24.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.474 ns ( 75.99 % ) " "Info: Total interconnect delay = 5.474 ns ( 75.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.204 ns" { RstN RstN~input mod:inst4|rposition[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.204 ns" { RstN RstN~input mod:inst4|rposition[17] } { 0.000ns 0.000ns 5.474ns } { 0.000ns 0.921ns 0.809ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.026 ns + " "Info: + Micro setup delay of destination is -0.026 ns" {  } { { "mod.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/mod.v" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clkin altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] -3.874 ns - " "Info: - Offset between input clock \"clkin\" and output clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" is -3.874 ns" {  } { { "original_signal.bdf" "" { Schematic "E:/Graduation_Design/Quartus/original_signal/original_signal.bdf" { { -16 8 176 0 "clkin" "" } } } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] destination 4.321 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" to destination register is 4.321 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.393 ns) + CELL(0.000 ns) 2.393 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl 2 COMB CLKCTRL_G3 579 " "Info: 2: + IC(2.393 ns) + CELL(0.000 ns) = 2.393 ns; Loc. = CLKCTRL_G3; Fanout = 579; COMB Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.690 ns) 4.321 ns mod:inst4\|rposition\[17\] 3 REG FF_X43_Y11_N31 3 " "Info: 3: + IC(1.238 ns) + CELL(0.690 ns) = 4.321 ns; Loc. = FF_X43_Y11_N31; Fanout = 3; REG Node = 'mod:inst4\|rposition\[17\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.928 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl mod:inst4|rposition[17] } "NODE_NAME" } } { "mod.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/mod.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.690 ns ( 15.97 % ) " "Info: Total cell delay = 0.690 ns ( 15.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.631 ns ( 84.03 % ) " "Info: Total interconnect delay = 3.631 ns ( 84.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.321 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl mod:inst4|rposition[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.321 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl mod:inst4|rposition[17] } { 0.000ns 2.393ns 1.238ns } { 0.000ns 0.000ns 0.690ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.204 ns" { RstN RstN~input mod:inst4|rposition[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.204 ns" { RstN RstN~input mod:inst4|rposition[17] } { 0.000ns 0.000ns 5.474ns } { 0.000ns 0.921ns 0.809ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.321 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl mod:inst4|rposition[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.321 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl mod:inst4|rposition[17] } { 0.000ns 2.393ns 1.238ns } { 0.000ns 0.000ns 0.690ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}