adder_8bit.v

verilog for full_adder

module adder_8bit(Cin,A0,A1,A2,A3,A4,A5,A6,A7,B0,B1,B2,B3,B4,B5,B6,B7,S0,S1,S2,S3,S4,S5,S6,S7,Cout);
input	A0,A1,A2,A3,A4,A5,A6,A7,B0,B1,B2,B3,B4,B5,B6,B7,Cin;
output	S0,S1,S2,S3,S4,S5,S6,S7,Cout;
wire	xor_1,xor_2,xor_3,xor_4,xor_5,xor_6,xor_7,xor_8;
wire	nand_1,nand_2,nand_3,nand_4,nand_5,nand_6,nand_7,nand_8,nand_9,nand_10,nand_11,nand_12,nand_13,nand_14,nand_15,nand_16,nand_17,nand_18,nand_19,nand_20,nand_21,nand_22,nand_23;

assign	xor_1=A0 ^ B0;
assign	nand_1=~(A0 & B0);
assign	nand_2=~(xor_1 & Cin);
assign	S0=Cin ^ xor_1;
assign	nand_3=~(nand_1 & nand_2);

assign	xor_2=A1 ^ B1;
assign	nand_4=~(A1 & B1);
assign	nand_5=~(xor_2 & nand_3);
assign	S1=nand_3^xor_2;
assign	nand_6=~(nand_4 & nand_5);

assign	xor_3=A2 ^ B2;
assign	nand_7=~(A2 & B2);
assign	nand_8=~(xor_3 & nand_6);
assign	S2=nand_6 ^ xor_3;
assign	nand_9=~(nand_7 & nand_8);

assign	xor_4=A3 ^ B3;
assign	nand_10=~(A3 & B3);
assign	nand_11=~(xor_4 & nand_9);
assign	S3=nand_9 ^ xor_4;
assign	nand_12=~(nand_10 & nand_11);

assign	xor_5=A4 ^ B4;
assign	nand_13=~(A4 & B4);
assign	nand_14=~(xor_5 & nand_12);
assign	S4=nand_12 ^ xor_5;
assign	nand_15=~(nand_13 & nand_14);

assign	xor_6=A5 ^ B5;
assign	nand_16=~(A5 & B5);
assign	nand_17=~(xor_6 & nand_15);
assign	S5=nand_15 ^ xor_6;
assign	nand_18=~(nand_16 & nand_17);

assign	xor_7=A6 ^ B6;
assign	nand_19=~(A6 & B6);
assign	nand_20=~(xor_7 & nand_18);
assign	S6=nand_18 ^ xor_7;
assign	nand_21=~(nand_19 & nand_20);

assign	xor_8=A7 ^ B7;
assign	nand_22=~(A7 & B7);
assign	nand_23=~(xor_8 & nand_21);
assign	S7=nand_21 ^ xor_8;
assign	Cout=~(nand_22 & nand_23);

endmodule