adder_4_bit.txt

来自「verilog for full_adder」· 文本 代码 · 共 11 行

module adder_4_bit (c , sum, a , b);
input a, b;
output c, sum;
wire [3:0] a, b, sum;
wire c0 , c1 , c2 , c ;
wire c0, c1, c2 ;
full_adder f1 (c0, sum[0] , a[0] , b[0] , b0);
full_adder f2 (c1, sum[1] , a[1] , b[1] , c0);
full_adder f3 (c2, sum[2] , a[2] , b[2] , c1);
full_adder f4 (c, sum[3] , a[3] , b[3] , c2);
endmodule