full_adder.txt

来自「verilog for full_adder」· 文本 代码 · 共 12 行

module full_adder (c_out , s , a , b , c);
input a, b, c;
wire a, b, c; 
output c_out , s;
wire c_out , s;
wire w1, w2, w3;
xor x1 (w1, a , b );
xor x2 (s, w1, c );
nand n1 (w2, a , b);
nand n2 (w3, w1 , c);
nand n3 (c_out , w3 , w2);
endmodule