tdma.vhd

用VHDL语言实现TDMA编码,简单

library ieee;
use ieee.std_logic_1164.all;
uns ieee.std_logic_unsigned.all;

entity TDMA IS
port(clk,ena,
a0,a1,a2,a3,a4,a5,a6,a7,
b0,b1,b2,b3,b4,b5,b6,b7,
c0,c1,c2,c3,c4,c5,c6,c7,
d0,d1,d2,d3,d4,d5,d6,d7:in std_logic;
s0,s1,s2,s3,fujiout:out std_logic);
end TDMA;

architecture bhv of TDMA is

component count16--调用计数器
port(clk:in std_logic;
     D,C,B,A:out std_logic);
end component;

component neimacs0--调用内码产生器
port(in0_8,in0_7,in0_6,n0_5,in0_4,in0_3,in0_2,in0_1,
     k3,k2,k1,sx0:in std_logic;
     out0:out std_logic);
end component;

component shixusuccessful--调用时序发生器
port(B:in std_logic;
     s0,s1,s2,s3:out std_logic);
end component;

component men--调用门器件
port(in1:in std_logic;
     out1:out std_logic);
end component;