miaobiao.tan.qmsg

来自「VHDL语言设计的秒表」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "ITDB_TH_RESULT" "second:inst2\|enmin reset clk 4.716 ns register " "Info: th for register \"second:inst2\|enmin\" (data pin = \"reset\", clock pin = \"clk\") is 4.716 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.941 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 13.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 13; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 40 0 168 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.935 ns) 8.502 ns msecond:inst1\|ensec 2 REG LC_X12_Y16_N9 10 " "Info: 2: + IC(6.098 ns) + CELL(0.935 ns) = 8.502 ns; Loc. = LC_X12_Y16_N9; Fanout = 10; REG Node = 'msecond:inst1\|ensec'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.033 ns" { clk msecond:inst1|ensec } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.728 ns) + CELL(0.711 ns) 13.941 ns second:inst2\|enmin 3 REG LC_X14_Y15_N9 9 " "Info: 3: + IC(4.728 ns) + CELL(0.711 ns) = 13.941 ns; Loc. = LC_X14_Y15_N9; Fanout = 9; REG Node = 'second:inst2\|enmin'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.439 ns" { msecond:inst1|ensec second:inst2|enmin } "NODE_NAME" } "" } } { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 22.34 % ) " "Info: Total cell delay = 3.115 ns ( 22.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.826 ns ( 77.66 % ) " "Info: Total interconnect delay = 10.826 ns ( 77.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "13.941 ns" { clk msecond:inst1|ensec second:inst2|enmin } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "13.941 ns" { clk clk~out0 msecond:inst1|ensec second:inst2|enmin } { 0.000ns 0.000ns 6.098ns 4.728ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.240 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.240 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_3 27 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 27; PIN Node = 'reset'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { reset } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 56 0 168 72 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.293 ns) + CELL(0.478 ns) 9.240 ns second:inst2\|enmin 2 REG LC_X14_Y15_N9 9 " "Info: 2: + IC(7.293 ns) + CELL(0.478 ns) = 9.240 ns; Loc. = LC_X14_Y15_N9; Fanout = 9; REG Node = 'second:inst2\|enmin'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.771 ns" { reset second:inst2|enmin } "NODE_NAME" } "" } } { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 21.07 % ) " "Info: Total cell delay = 1.947 ns ( 21.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.293 ns ( 78.93 % ) " "Info: Total interconnect delay = 7.293 ns ( 78.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "9.240 ns" { reset second:inst2|enmin } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.240 ns" { reset reset~out0 second:inst2|enmin } { 0.000ns 0.000ns 7.293ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "13.941 ns" { clk msecond:inst1|ensec second:inst2|enmin } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "13.941 ns" { clk clk~out0 msecond:inst1|ensec second:inst2|enmin } { 0.000ns 0.000ns 6.098ns 4.728ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "9.240 ns" { reset second:inst2|enmin } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.240 ns" { reset reset~out0 second:inst2|enmin } { 0.000ns 0.000ns 7.293ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 07 01:42:46 2008 " "Info: Processing ended: Sat Jun 07 01:42:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}