miaobiao.tan.qmsg

来自「VHDL语言设计的秒表」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 40 0 168 56 "clk" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clkdsp " "Info: Assuming node \"clkdsp\" is an undefined clock" {  } { { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 120 -24 144 136 "clkdsp" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkdsp" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "second:inst2\|enmin " "Info: Detected ripple clock \"second:inst2\|enmin\" as buffer" {  } { { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd" 7 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "second:inst2\|enmin" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "msecond:inst1\|ensec " "Info: Detected ripple clock \"msecond:inst1\|ensec\" as buffer" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "msecond:inst1\|ensec" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register msecond:inst1\|count\[1\] register msecond:inst1\|count\[5\] 225.73 MHz 4.43 ns Internal " "Info: Clock \"clk\" has Internal fmax of 225.73 MHz between source register \"msecond:inst1\|count\[1\]\" and destination register \"msecond:inst1\|count\[5\]\" (period= 4.43 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.169 ns + Longest register register " "Info: + Longest register to register delay is 4.169 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns msecond:inst1\|count\[1\] 1 REG LC_X12_Y16_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y16_N2; Fanout = 5; REG Node = 'msecond:inst1\|count\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { msecond:inst1|count[1] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.590 ns) 1.140 ns rtl~201 2 COMB LC_X12_Y16_N8 8 " "Info: 2: + IC(0.550 ns) + CELL(0.590 ns) = 1.140 ns; Loc. = LC_X12_Y16_N8; Fanout = 8; COMB Node = 'rtl~201'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.140 ns" { msecond:inst1|count[1] rtl~201 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.140 ns) + CELL(0.292 ns) 2.572 ns msecond:inst1\|count\[4\]~331 3 COMB LC_X12_Y16_N0 7 " "Info: 3: + IC(1.140 ns) + CELL(0.292 ns) = 2.572 ns; Loc. = LC_X12_Y16_N0; Fanout = 7; COMB Node = 'msecond:inst1\|count\[4\]~331'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.432 ns" { rtl~201 msecond:inst1|count[4]~331 } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(1.112 ns) 4.169 ns msecond:inst1\|count\[5\] 4 REG LC_X12_Y16_N6 6 " "Info: 4: + IC(0.485 ns) + CELL(1.112 ns) = 4.169 ns; Loc. = LC_X12_Y16_N6; Fanout = 6; REG Node = 'msecond:inst1\|count\[5\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.597 ns" { msecond:inst1|count[4]~331 msecond:inst1|count[5] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.994 ns ( 47.83 % ) " "Info: Total cell delay = 1.994 ns ( 47.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.175 ns ( 52.17 % ) " "Info: Total interconnect delay = 2.175 ns ( 52.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "4.169 ns" { msecond:inst1|count[1] rtl~201 msecond:inst1|count[4]~331 msecond:inst1|count[5] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "4.169 ns" { msecond:inst1|count[1] rtl~201 msecond:inst1|count[4]~331 msecond:inst1|count[5] } { 0.000ns 0.550ns 1.140ns 0.485ns } { 0.000ns 0.590ns 0.292ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.278 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 13; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 40 0 168 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns msecond:inst1\|count\[5\] 2 REG LC_X12_Y16_N6 6 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X12_Y16_N6; Fanout = 6; REG Node = 'msecond:inst1\|count\[5\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.809 ns" { clk msecond:inst1|count[5] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk msecond:inst1|count[5] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 msecond:inst1|count[5] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.278 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 13; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 40 0 168 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns msecond:inst1\|count\[1\] 2 REG LC_X12_Y16_N2 5 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X12_Y16_N2; Fanout = 5; REG Node = 'msecond:inst1\|count\[1\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.809 ns" { clk msecond:inst1|count[1] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk msecond:inst1|count[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 msecond:inst1|count[1] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk msecond:inst1|count[5] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 msecond:inst1|count[5] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk msecond:inst1|count[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 msecond:inst1|count[1] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "4.169 ns" { msecond:inst1|count[1] rtl~201 msecond:inst1|count[4]~331 msecond:inst1|count[5] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "4.169 ns" { msecond:inst1|count[1] rtl~201 msecond:inst1|count[4]~331 msecond:inst1|count[5] } { 0.000ns 0.550ns 1.140ns 0.485ns } { 0.000ns 0.590ns 0.292ns 1.112ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk msecond:inst1|count[5] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 msecond:inst1|count[5] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk msecond:inst1|count[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 msecond:inst1|count[1] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}