miaobiao.tan.qmsg

来自「VHDL语言设计的秒表」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clkdsp register register zhishi:inst\|count\[0\] zhishi:inst\|count\[2\] 275.03 MHz Internal " "Info: Clock \"clkdsp\" Internal fmax is restricted to 275.03 MHz between source register \"zhishi:inst\|count\[0\]\" and destination register \"zhishi:inst\|count\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.343 ns + Longest register register " "Info: + Longest register to register delay is 1.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns zhishi:inst\|count\[0\] 1 REG LC_X13_Y16_N1 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y16_N1; Fanout = 12; REG Node = 'zhishi:inst\|count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { zhishi:inst|count[0] } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.738 ns) 1.343 ns zhishi:inst\|count\[2\] 2 REG LC_X13_Y16_N7 9 " "Info: 2: + IC(0.605 ns) + CELL(0.738 ns) = 1.343 ns; Loc. = LC_X13_Y16_N7; Fanout = 9; REG Node = 'zhishi:inst\|count\[2\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.343 ns" { zhishi:inst|count[0] zhishi:inst|count[2] } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 54.95 % ) " "Info: Total cell delay = 0.738 ns ( 54.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.605 ns ( 45.05 % ) " "Info: Total interconnect delay = 0.605 ns ( 45.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.343 ns" { zhishi:inst|count[0] zhishi:inst|count[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.343 ns" { zhishi:inst|count[0] zhishi:inst|count[2] } { 0.000ns 0.605ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkdsp destination 7.027 ns + Shortest register " "Info: + Shortest clock path from clock \"clkdsp\" to destination register is 7.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkdsp 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'clkdsp'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clkdsp } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 120 -24 144 136 "clkdsp" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.847 ns) + CELL(0.711 ns) 7.027 ns zhishi:inst\|count\[2\] 2 REG LC_X13_Y16_N7 9 " "Info: 2: + IC(4.847 ns) + CELL(0.711 ns) = 7.027 ns; Loc. = LC_X13_Y16_N7; Fanout = 9; REG Node = 'zhishi:inst\|count\[2\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.558 ns" { clkdsp zhishi:inst|count[2] } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.02 % ) " "Info: Total cell delay = 2.180 ns ( 31.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.847 ns ( 68.98 % ) " "Info: Total interconnect delay = 4.847 ns ( 68.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.027 ns" { clkdsp zhishi:inst|count[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.027 ns" { clkdsp clkdsp~out0 zhishi:inst|count[2] } { 0.000ns 0.000ns 4.847ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkdsp source 7.027 ns - Longest register " "Info: - Longest clock path from clock \"clkdsp\" to source register is 7.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkdsp 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'clkdsp'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clkdsp } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 120 -24 144 136 "clkdsp" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.847 ns) + CELL(0.711 ns) 7.027 ns zhishi:inst\|count\[0\] 2 REG LC_X13_Y16_N1 12 " "Info: 2: + IC(4.847 ns) + CELL(0.711 ns) = 7.027 ns; Loc. = LC_X13_Y16_N1; Fanout = 12; REG Node = 'zhishi:inst\|count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.558 ns" { clkdsp zhishi:inst|count[0] } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.02 % ) " "Info: Total cell delay = 2.180 ns ( 31.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.847 ns ( 68.98 % ) " "Info: Total interconnect delay = 4.847 ns ( 68.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.027 ns" { clkdsp zhishi:inst|count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.027 ns" { clkdsp clkdsp~out0 zhishi:inst|count[0] } { 0.000ns 0.000ns 4.847ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.027 ns" { clkdsp zhishi:inst|count[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.027 ns" { clkdsp clkdsp~out0 zhishi:inst|count[2] } { 0.000ns 0.000ns 4.847ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.027 ns" { clkdsp zhishi:inst|count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.027 ns" { clkdsp clkdsp~out0 zhishi:inst|count[0] } { 0.000ns 0.000ns 4.847ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.343 ns" { zhishi:inst|count[0] zhishi:inst|count[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "1.343 ns" { zhishi:inst|count[0] zhishi:inst|count[2] } { 0.000ns 0.605ns } { 0.000ns 0.738ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.027 ns" { clkdsp zhishi:inst|count[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.027 ns" { clkdsp clkdsp~out0 zhishi:inst|count[2] } { 0.000ns 0.000ns 4.847ns } { 0.000ns 1.469ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.027 ns" { clkdsp zhishi:inst|count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "7.027 ns" { clkdsp clkdsp~out0 zhishi:inst|count[0] } { 0.000ns 0.000ns 4.847ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { zhishi:inst|count[2] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { zhishi:inst|count[2] } {  } {  } } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 19 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "msecond:inst1\|count\[3\] set clk 1.389 ns register " "Info: tsu for register \"msecond:inst1\|count\[3\]\" (data pin = \"set\", clock pin = \"clk\") is 1.389 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.630 ns + Longest pin register " "Info: + Longest pin to register delay is 9.630 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns set 1 PIN PIN_4 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_4; Fanout = 15; PIN Node = 'set'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { set } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 72 0 168 88 "set" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.294 ns) + CELL(0.867 ns) 9.630 ns msecond:inst1\|count\[3\] 2 REG LC_X12_Y16_N4 4 " "Info: 2: + IC(7.294 ns) + CELL(0.867 ns) = 9.630 ns; Loc. = LC_X12_Y16_N4; Fanout = 4; REG Node = 'msecond:inst1\|count\[3\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.161 ns" { set msecond:inst1|count[3] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 24.26 % ) " "Info: Total cell delay = 2.336 ns ( 24.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.294 ns ( 75.74 % ) " "Info: Total interconnect delay = 7.294 ns ( 75.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "9.630 ns" { set msecond:inst1|count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.630 ns" { set set~out0 msecond:inst1|count[3] } { 0.000ns 0.000ns 7.294ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.278 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.278 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 13; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 40 0 168 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.711 ns) 8.278 ns msecond:inst1\|count\[3\] 2 REG LC_X12_Y16_N4 4 " "Info: 2: + IC(6.098 ns) + CELL(0.711 ns) = 8.278 ns; Loc. = LC_X12_Y16_N4; Fanout = 4; REG Node = 'msecond:inst1\|count\[3\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "6.809 ns" { clk msecond:inst1|count[3] } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 26.33 % ) " "Info: Total cell delay = 2.180 ns ( 26.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.098 ns ( 73.67 % ) " "Info: Total interconnect delay = 6.098 ns ( 73.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk msecond:inst1|count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 msecond:inst1|count[3] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "9.630 ns" { set msecond:inst1|count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.630 ns" { set set~out0 msecond:inst1|count[3] } { 0.000ns 0.000ns 7.294ns } { 0.000ns 1.469ns 0.867ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "8.278 ns" { clk msecond:inst1|count[3] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.278 ns" { clk clk~out0 msecond:inst1|count[3] } { 0.000ns 0.000ns 6.098ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led\[4\] minute:inst3\|count\[0\] 38.105 ns register " "Info: tco from clock \"clk\" to destination pin \"led\[4\]\" through register \"minute:inst3\|count\[0\]\" is 38.105 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 19.670 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 19.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_2 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 13; CLK Node = 'clk'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { clk } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 40 0 168 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.935 ns) 8.502 ns msecond:inst1\|ensec 2 REG LC_X12_Y16_N9 10 " "Info: 2: + IC(6.098 ns) + CELL(0.935 ns) = 8.502 ns; Loc. = LC_X12_Y16_N9; Fanout = 10; REG Node = 'msecond:inst1\|ensec'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "7.033 ns" { clk msecond:inst1|ensec } "NODE_NAME" } "" } } { "msecond.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/msecond.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.728 ns) + CELL(0.935 ns) 14.165 ns second:inst2\|enmin 3 REG LC_X14_Y15_N9 9 " "Info: 3: + IC(4.728 ns) + CELL(0.935 ns) = 14.165 ns; Loc. = LC_X14_Y15_N9; Fanout = 9; REG Node = 'second:inst2\|enmin'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.663 ns" { msecond:inst1|ensec second:inst2|enmin } "NODE_NAME" } "" } } { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/second.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.794 ns) + CELL(0.711 ns) 19.670 ns minute:inst3\|count\[0\] 4 REG LC_X13_Y17_N1 5 " "Info: 4: + IC(4.794 ns) + CELL(0.711 ns) = 19.670 ns; Loc. = LC_X13_Y17_N1; Fanout = 5; REG Node = 'minute:inst3\|count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "5.505 ns" { second:inst2|enmin minute:inst3|count[0] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 20.59 % ) " "Info: Total cell delay = 4.050 ns ( 20.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.620 ns ( 79.41 % ) " "Info: Total interconnect delay = 15.620 ns ( 79.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "19.670 ns" { clk msecond:inst1|ensec second:inst2|enmin minute:inst3|count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "19.670 ns" { clk clk~out0 msecond:inst1|ensec second:inst2|enmin minute:inst3|count[0] } { 0.000ns 0.000ns 6.098ns 4.728ns 4.794ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.211 ns + Longest register pin " "Info: + Longest register to pin delay is 18.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute:inst3\|count\[0\] 1 REG LC_X13_Y17_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y17_N1; Fanout = 5; REG Node = 'minute:inst3\|count\[0\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "" { minute:inst3|count[0] } "NODE_NAME" } "" } } { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/minute.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.295 ns) + CELL(0.442 ns) 1.737 ns zhishi:inst\|daout\[0\]~933 2 COMB LC_X13_Y16_N5 1 " "Info: 2: + IC(1.295 ns) + CELL(0.442 ns) = 1.737 ns; Loc. = LC_X13_Y16_N5; Fanout = 1; COMB Node = 'zhishi:inst\|daout\[0\]~933'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "1.737 ns" { minute:inst3|count[0] zhishi:inst|daout[0]~933 } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.442 ns) 2.624 ns zhishi:inst\|daout\[0\]~936 3 COMB LC_X13_Y16_N4 12 " "Info: 3: + IC(0.445 ns) + CELL(0.442 ns) = 2.624 ns; Loc. = LC_X13_Y16_N4; Fanout = 12; COMB Node = 'zhishi:inst\|daout\[0\]~936'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.887 ns" { zhishi:inst|daout[0]~933 zhishi:inst|daout[0]~936 } "NODE_NAME" } "" } } { "zhishi.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/zhishi.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.277 ns) + CELL(0.590 ns) 6.491 ns deled:inst5\|led~1150 4 COMB LC_X2_Y5_N5 3 " "Info: 4: + IC(3.277 ns) + CELL(0.590 ns) = 6.491 ns; Loc. = LC_X2_Y5_N5; Fanout = 3; COMB Node = 'deled:inst5\|led~1150'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.867 ns" { zhishi:inst|daout[0]~936 deled:inst5|led~1150 } "NODE_NAME" } "" } } { "deled.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/deled.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.999 ns) + CELL(0.590 ns) 10.080 ns deled:inst5\|led~1151 5 COMB LC_X13_Y15_N3 1 " "Info: 5: + IC(2.999 ns) + CELL(0.590 ns) = 10.080 ns; Loc. = LC_X13_Y15_N3; Fanout = 1; COMB Node = 'deled:inst5\|led~1151'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.589 ns" { deled:inst5|led~1150 deled:inst5|led~1151 } "NODE_NAME" } "" } } { "deled.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/deled.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.442 ns) 10.922 ns deled:inst5\|led~1152 6 COMB LC_X13_Y15_N5 2 " "Info: 6: + IC(0.400 ns) + CELL(0.442 ns) = 10.922 ns; Loc. = LC_X13_Y15_N5; Fanout = 2; COMB Node = 'deled:inst5\|led~1152'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "0.842 ns" { deled:inst5|led~1151 deled:inst5|led~1152 } "NODE_NAME" } "" } } { "deled.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/deled.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.079 ns) + CELL(0.292 ns) 14.293 ns deled:inst5\|led~1154 7 COMB LC_X2_Y5_N8 1 " "Info: 7: + IC(3.079 ns) + CELL(0.292 ns) = 14.293 ns; Loc. = LC_X2_Y5_N8; Fanout = 1; COMB Node = 'deled:inst5\|led~1154'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.371 ns" { deled:inst5|led~1152 deled:inst5|led~1154 } "NODE_NAME" } "" } } { "deled.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/miaobiao/deled.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.794 ns) + CELL(2.124 ns) 18.211 ns led\[4\] 8 PIN PIN_49 0 " "Info: 8: + IC(1.794 ns) + CELL(2.124 ns) = 18.211 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'led\[4\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "3.918 ns" { deled:inst5|led~1154 led[4] } "NODE_NAME" } "" } } { "miaobiao.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/miaobiao/miaobiao.bdf" { { 160 864 1040 176 "led\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.922 ns ( 27.03 % ) " "Info: Total cell delay = 4.922 ns ( 27.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.289 ns ( 72.97 % ) " "Info: Total interconnect delay = 13.289 ns ( 72.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "18.211 ns" { minute:inst3|count[0] zhishi:inst|daout[0]~933 zhishi:inst|daout[0]~936 deled:inst5|led~1150 deled:inst5|led~1151 deled:inst5|led~1152 deled:inst5|led~1154 led[4] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "18.211 ns" { minute:inst3|count[0] zhishi:inst|daout[0]~933 zhishi:inst|daout[0]~936 deled:inst5|led~1150 deled:inst5|led~1151 deled:inst5|led~1152 deled:inst5|led~1154 led[4] } { 0.000ns 1.295ns 0.445ns 3.277ns 2.999ns 0.400ns 3.079ns 1.794ns } { 0.000ns 0.442ns 0.442ns 0.590ns 0.590ns 0.442ns 0.292ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "19.670 ns" { clk msecond:inst1|ensec second:inst2|enmin minute:inst3|count[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "19.670 ns" { clk clk~out0 msecond:inst1|ensec second:inst2|enmin minute:inst3|count[0] } { 0.000ns 0.000ns 6.098ns 4.728ns 4.794ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "miaobiao" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/miaobiao/db/miaobiao.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/miaobiao/" "" "18.211 ns" { minute:inst3|count[0] zhishi:inst|daout[0]~933 zhishi:inst|daout[0]~936 deled:inst5|led~1150 deled:inst5|led~1151 deled:inst5|led~1152 deled:inst5|led~1154 led[4] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "18.211 ns" { minute:inst3|count[0] zhishi:inst|daout[0]~933 zhishi:inst|daout[0]~936 deled:inst5|led~1150 deled:inst5|led~1151 deled:inst5|led~1152 deled:inst5|led~1154 led[4] } { 0.000ns 1.295ns 0.445ns 3.277ns 2.999ns 0.400ns 3.079ns 1.794ns } { 0.000ns 0.442ns 0.442ns 0.590ns 0.590ns 0.442ns 0.292ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}