fast_alu_unpack.v

用verilog写的

// fast_alu_unpack.v 

module fast_alu_unpack(
	input clock,
	input clken,
	input reset,
	input [31:0] fp,		// IEEE standard single-precision float
	output reg sgn,			// Sign bit: 0==positive, 1==negative
	output reg [7:0] exp,	// Exponent field with +127 bias
	output reg [23:0] man	// Mantissa field where binary point is between bits 23 and 22
);

// Note: output is always normalized (man[23]==1) except for zero where both exp and man are zero.

always @(posedge clock or posedge reset)
	if(reset) begin
		sgn <= 1'b0;
		exp <= 8'b0;
		man <= 24'b0;
	end else if(clken) begin
		sgn <= fp[31];
		exp <= fp[30:23];
		man <= (fp[30:23] > 0) ? {1'b1, fp[22:0]} : fp[22] ? {fp[22:0], 1'b0} : 24'b0;
	end

endmodule