fast_alu_log10.v

用verilog写的

// fast_alu_log10.v 

module fast_alu_log10(
	input clock,
	input clken,
	input reset,
	input start,
	input [31:0] dataa,
	output reg [31:0] result,
	output done
);
`define _INF 32'hFF800000
`define INF  32'h7F800000
`define NaN  32'h7FC00000

reg [4:0] start_d;
wire sgn_a;
wire [7:0] exp_a;
wire [23:0] man_a;
wire [15:0] log_m;

fast_alu_unpack unpack_a(
	.clock(clock),
	.clken(clken),
	.reset(reset),
	.fp(dataa),
	.sgn(sgn_a),
	.exp(exp_a),
	.man(man_a)
);
wire [22:0] man_a_round = &man_a[22:13] ? man_a[22:0] : man_a[22:0] + 23'h1000; // round
wire [9:0] man_addr = man_a_round[22:13];
 
log10lut lut_0 (
	.address( man_addr ),
	.clock( clock ),
	.q( log_m ) 
);
wire sgn_r = exp_a < 8'd127;

wire [7:0] exp1 = exp_a - 8'd127;
wire [30:0] sum1 = {9'b0, log_m, 6'b0} + exp1 * 22'd2525223;

wire [7:0] exp2 = 8'd127 - exp_a;
wire [30:0] sum2 = exp2 * 22'd2525223 - {8'h0, log_m, 6'h0};
wire [30:0] sum = sgn_r ? sum2 : sum1;

wire [4:0] nz;
countlz31 countlz31(.x(sum), .n(nz));

wire [30:0] man_t = sum << nz;
wire [30:0] man_r_round = &man_t[30:7] ? man_t[30:0] : man_t[30:0] + 31'h40; // round
wire [23:0] man_r = man_r_round[30:7];
wire [7:0] exp_r = 8'd134 - nz;
wire [31:0] result_t;

wire is_zero = ~(|exp_a | |man_a[22:0]);
wire is_inf  = &exp_a & ~|man_a[22:0];
wire is_nan  = &exp_a & |man_a[22:0];
	 
always @(posedge clock or posedge reset)
	if(reset) begin
		start_d <= 5'b0;
		result <= 32'b0;
	end else if(clken) begin
		start_d <= {start_d[3:0], start};
		
		if( sgn_a | is_zero )
			result <= `_INF;
		else if( is_inf )
			result <= `INF;
		else if( is_nan )
			result <= `NaN;
		else
			result <= result_r;
	end
	
wire [31:0] result_r;
reg [31:0] result_r2;

fast_alu_pack pack(
	.sgn(sgn_r),
	.exp(exp_r),
	.man(man_r),
	.fp(result_r)
);

assign done = start_d[4];

endmodule