_primary.vhd

来自「用4位十进制计数器对用户输入时钟信号进行计数」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity CLKLOCK is
    generic(
        CLOCKBOOST      : integer := 1;
        INPUT_FREQUENCY : real    := 50.000000;
        TPD             : integer := 0
    );
    port(
        OUTCLK          : out    vl_logic;
        INCLK           : in     vl_logic
    );
end CLKLOCK;