_primary.vhd

来自「用4位十进制计数器对用户输入时钟信号进行计数」· VHDL 代码 · 共 7 行

library verilog;
use verilog.vl_types.all;
entity PRIM_DFFE1 is
    // This module cannot be connected to from
    // VHDL because it has unnamed ports.
end PRIM_DFFE1;