_primary.vhd

来自「用4位十进制计数器对用户输入时钟信号进行计数」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity DFF5_frequen_cout is
    port(
        Q               : out    vl_logic;
        D               : in     vl_logic;
        CLK             : in     vl_logic;
        CLRN            : in     vl_logic;
        PRN             : in     vl_logic
    );
end DFF5_frequen_cout;