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📄 altsyncram_mea1.tdf

📁 EP2C CYCONLY 系列的FPGA时钟测试程序
💻 TDF
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--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" ENABLE_RUNTIME_MOD="YES" INIT_FILE="../../sin_gen14/sin_70_gen.mif" INSTANCE_NAME="rom" LOW_POWER_MODE="AUTO" NUMWORDS_A=32 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=14 WIDTH_BYTEENA_A=1 WIDTHAD_A=5 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.1 cbx_altsyncram 2007:03:22:08:29:24:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_lpm_mux 2006:11:21:10:27:10:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_stratixiii 2007:03:13:14:47:12:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION altsyncram_am92 (address_a[4..0], address_b[4..0], clock0, clock1, data_b[13..0], wren_b)
RETURNS ( q_a[13..0], q_b[13..0]);
FUNCTION sld_mod_ram_rom (data_read[13..0])
WITH ( 	CVALUE,	IS_DATA_IN_RAM,	IS_READABLE,	NODE_NAME,	NUMWORDS,	SHIFT_COUNT_BITS,	WIDTH_WORD,	WIDTHAD) 
RETURNS ( address[4..0], data_write[13..0], enable_write, tck_usr);

--synthesis_resources = M4K 1 sld_mod_ram_rom 1 
SUBDESIGN altsyncram_mea1
( 
	address_a[4..0]	:	input;
	clock0	:	input;
	q_a[13..0]	:	output;
) 
VARIABLE 
	altsyncram1 : altsyncram_am92;
	mgl_prim2 : sld_mod_ram_rom
		WITH (
			CVALUE = "00000000000000",
			IS_DATA_IN_RAM = 1,
			IS_READABLE = 1,
			NODE_NAME = 1919905024,
			NUMWORDS = 32,
			SHIFT_COUNT_BITS = 4,
			WIDTH_WORD = 14,
			WIDTHAD = 5
		);

BEGIN 
	altsyncram1.address_a[] = address_a[];
	altsyncram1.address_b[] = mgl_prim2.address[];
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = mgl_prim2.tck_usr;
	altsyncram1.data_b[] = mgl_prim2.data_write[];
	altsyncram1.wren_b = mgl_prim2.enable_write;
	mgl_prim2.data_read[] = altsyncram1.q_b[];
	q_a[] = altsyncram1.q_a[];
END;
--VALID FILE

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