half_ad.map.qmsg

4位全加器设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 23 16:17:07 2009 " "Info: Processing started: Mon Mar 23 16:17:07 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off half_ad -c half_ad " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off half_ad -c half_ad" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "adder_4 " "Warning: Ignored assignments for entity \"adder_4\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -section_id Top " "Warning: Assignment of entity set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top is ignored" {  } {  } 0 0 "Assignment of entity %1!s! is ignored" 0 0}  } {  } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "half_ad.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file half_ad.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 half_ad " "Info: Found entity 1: half_ad" {  } { { "half_ad.bdf" "" { Schematic "H:/project/add/half_ad.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder " "Info: Found entity 1: adder" {  } { { "adder.bdf" "" { Schematic "H:/project/add/adder.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder_4.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adder_4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adder_4 " "Info: Found entity 1: adder_4" {  } { { "adder_4.bdf" "" { Schematic "H:/project/add/adder_4.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adder_4 " "Info: Elaborating entity \"adder_4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "half_ad half_ad:inst " "Info: Elaborating entity \"half_ad\" for hierarchy \"half_ad:inst\"" {  } { { "adder_4.bdf" "inst" { Schematic "H:/project/add/adder_4.bdf" { { -8 192 288 88 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder adder:inst1 " "Info: Elaborating entity \"adder\" for hierarchy \"adder:inst1\"" {  } { { "adder_4.bdf" "inst1" { Schematic "H:/project/add/adder_4.bdf" { { 112 192 288 208 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "20 " "Info: Implemented 20 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "7 " "Info: Implemented 7 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 23 16:17:08 2009 " "Info: Processing ended: Mon Mar 23 16:17:08 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}