half_ad.tan.qmsg

4位全加器设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 23 16:17:19 2009 " "Info: Processing started: Mon Mar 23 16:17:19 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off half_ad -c half_ad --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off half_ad -c half_ad --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] s\[3\] 12.453 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"s\[3\]\" is 12.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns a\[0\] 1 PIN PIN_235 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_235; Fanout = 3; PIN Node = 'a\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "adder_4.bdf" "" { Schematic "H:/project/add/adder_4.bdf" { { 168 -88 80 184 "a\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.133 ns) + CELL(0.590 ns) 7.198 ns adder:inst1\|inst2~3 2 COMB LC_X4_Y26_N9 2 " "Info: 2: + IC(5.133 ns) + CELL(0.590 ns) = 7.198 ns; Loc. = LC_X4_Y26_N9; Fanout = 2; COMB Node = 'adder:inst1\|inst2~3'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.723 ns" { a[0] adder:inst1|inst2~3 } "NODE_NAME" } } { "adder.bdf" "" { Schematic "H:/project/add/adder.bdf" { { 304 408 472 352 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.292 ns) 7.939 ns adder:inst2\|inst2~70 3 COMB LC_X4_Y26_N6 2 " "Info: 3: + IC(0.449 ns) + CELL(0.292 ns) = 7.939 ns; Loc. = LC_X4_Y26_N6; Fanout = 2; COMB Node = 'adder:inst2\|inst2~70'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.741 ns" { adder:inst1|inst2~3 adder:inst2|inst2~70 } "NODE_NAME" } } { "adder.bdf" "" { Schematic "H:/project/add/adder.bdf" { { 304 408 472 352 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.114 ns) 8.501 ns adder:inst3\|half_ad:inst1\|inst1 4 COMB LC_X4_Y26_N5 1 " "Info: 4: + IC(0.448 ns) + CELL(0.114 ns) = 8.501 ns; Loc. = LC_X4_Y26_N5; Fanout = 1; COMB Node = 'adder:inst3\|half_ad:inst1\|inst1'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.562 ns" { adder:inst2|inst2~70 adder:inst3|half_ad:inst1|inst1 } "NODE_NAME" } } { "half_ad.bdf" "" { Schematic "H:/project/add/half_ad.bdf" { { 120 240 304 168 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.828 ns) + CELL(2.124 ns) 12.453 ns s\[3\] 5 PIN PIN_3 0 " "Info: 5: + IC(1.828 ns) + CELL(2.124 ns) = 12.453 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 's\[3\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.952 ns" { adder:inst3|half_ad:inst1|inst1 s[3] } "NODE_NAME" } } { "adder_4.bdf" "" { Schematic "H:/project/add/adder_4.bdf" { { 192 472 648 208 "s\[4..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.595 ns ( 36.90 % ) " "Info: Total cell delay = 4.595 ns ( 36.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.858 ns ( 63.10 % ) " "Info: Total interconnect delay = 7.858 ns ( 63.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "12.453 ns" { a[0] adder:inst1|inst2~3 adder:inst2|inst2~70 adder:inst3|half_ad:inst1|inst1 s[3] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "12.453 ns" { a[0] a[0]~out0 adder:inst1|inst2~3 adder:inst2|inst2~70 adder:inst3|half_ad:inst1|inst1 s[3] } { 0.000ns 0.000ns 5.133ns 0.449ns 0.448ns 1.828ns } { 0.000ns 1.475ns 0.590ns 0.292ns 0.114ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 23 16:17:20 2009 " "Info: Processing ended: Mon Mar 23 16:17:20 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}