half_ad.vhd

4位全加器设计

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 6.1 Build 201 11/27/2006 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY half_ad IS 
	port
	(
		a :  IN  STD_LOGIC;
		b :  IN  STD_LOGIC;
		so :  OUT  STD_LOGIC;
		co :  OUT  STD_LOGIC
	);
END half_ad;

ARCHITECTURE bdf_type OF half_ad IS 



BEGIN 



co <= b AND a;

so <= b XOR a;

END;