minute.vhd

来自「该文件是用VHDL变成实现的数字钟程序」· VHDL 代码 · 共 37 行

library ieee; --fenjishu
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minute is
port(clk,reset:in std_logic;
     min1,min2:out std_logic_vector(3 downto 0);
     carry:out std_logic);
end;
architecture rt2 of minute is
signal min1_t,min2_t:std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if reset='1' then
min1_t<="0000";
min2_t<="0000";
elsif clk'event and clk='1' then
if min1_t="1001" then
   min1_t<="0000";
if min2_t="0101" then
   min2_t<="0000";
else
min2_t<=min2_t+1;
end if;
else 
min1_t<=min1_t+1;
end if;
if min1_t="1001" and min2_t="0101" then
carry<='1';
else
carry<='0';
end if;
end if;
min1<=min1_t;
min2<=min2_t;
end process;
end rt2;