hour.vhd

来自「该文件是用VHDL变成实现的数字钟程序」· VHDL 代码 · 共 36 行

library ieee; --xiaoshijishu
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(clk,reset:in std_logic;
     hour1,hour2:out std_logic_vector(3 downto 0));
     end;
architecture rt3 of hour is
signal hour1_t,hour2_t:std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if reset='1' then
hour1_t<="0000";
hour2_t<="0000";
elsif clk'event and clk='1' then
if hour1_t="0011"and hour2_t<="0010" then
   hour1_t<="0000";
   hour2_t<="0000";
else
if hour1_t="1001" then
   hour1_t<="0000";
if hour2_t="0010" then
   hour2_t<="0000";
else
hour2_t<=hour2_t+1;
end if;
else 
hour1_t<=hour1_t+1;
end if;
end if;
end if;
hour1<=hour1_t;
hour2<=hour2_t;
end process;
end rt3;