szsz.fit.summary

该文件是用VHDL变成实现的数字钟程序

Fitter Status : Successful - Thu Nov 13 16:13:00 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Web Edition
Revision Name : szsz
Top-level Entity Name : hour
Family : ACEX1K
Device : EP1K100QC208-3
Timing Models : Final
Total logic elements : 15 / 4,992 ( < 1 % )
Total pins : 10 / 147 ( 7 % )
Total memory bits : 0 / 49,152 ( 0 % )
Total PLLs : 0