szsz.map.summary

该文件是用VHDL变成实现的数字钟程序

Analysis & Synthesis Status : Successful - Thu Nov 13 16:12:33 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Web Edition
Revision Name : szsz
Top-level Entity Name : hour
Family : ACEX1K
Total logic elements : 15
Total pins : 10
Total memory bits : 0
Total PLLs : 0