clock.tan.qmsg

用verilog实现的数字跑表

{ "Info" "ITDB_TH_RESULT" "MSL\[2\] pause clk_odd -4.617 ns register " "Info: th for register \"MSL\[2\]\" (data pin = \"pause\", clock pin = \"clk_odd\") is -4.617 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_odd destination 3.135 ns + Longest register " "Info: + Longest clock path from clock \"clk_odd\" to destination register is 3.135 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.160 ns) 1.160 ns clk_odd 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.160 ns) = 1.160 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk_odd'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_odd } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.000 ns) 1.411 ns clk_odd~clkctrl 2 COMB CLKCTRL_G15 8 " "Info: 2: + IC(0.251 ns) + CELL(0.000 ns) = 1.411 ns; Loc. = CLKCTRL_G15; Fanout = 8; COMB Node = 'clk_odd~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.251 ns" { clk_odd clk_odd~clkctrl } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.058 ns) + CELL(0.666 ns) 3.135 ns MSL\[2\] 3 REG LCFF_X24_Y12_N13 5 " "Info: 3: + IC(1.058 ns) + CELL(0.666 ns) = 3.135 ns; Loc. = LCFF_X24_Y12_N13; Fanout = 5; REG Node = 'MSL\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.724 ns" { clk_odd~clkctrl MSL[2] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.826 ns ( 58.25 % ) " "Info: Total cell delay = 1.826 ns ( 58.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.309 ns ( 41.75 % ) " "Info: Total interconnect delay = 1.309 ns ( 41.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.135 ns" { clk_odd clk_odd~clkctrl MSL[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.135 ns" { clk_odd {} clk_odd~combout {} clk_odd~clkctrl {} MSL[2] {} } { 0.000ns 0.000ns 0.251ns 1.058ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 29 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.058 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.058 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.015 ns) 1.015 ns pause 1 PIN PIN_39 6 " "Info: 1: + IC(0.000 ns) + CELL(1.015 ns) = 1.015 ns; Loc. = PIN_39; Fanout = 6; PIN Node = 'pause'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pause } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.284 ns) + CELL(0.651 ns) 7.950 ns MSL\[2\]~88 2 COMB LCCOMB_X24_Y12_N12 1 " "Info: 2: + IC(6.284 ns) + CELL(0.651 ns) = 7.950 ns; Loc. = LCCOMB_X24_Y12_N12; Fanout = 1; COMB Node = 'MSL\[2\]~88'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.935 ns" { pause MSL[2]~88 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.058 ns MSL\[2\] 3 REG LCFF_X24_Y12_N13 5 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.058 ns; Loc. = LCFF_X24_Y12_N13; Fanout = 5; REG Node = 'MSL\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { MSL[2]~88 MSL[2] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.774 ns ( 22.02 % ) " "Info: Total cell delay = 1.774 ns ( 22.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.284 ns ( 77.98 % ) " "Info: Total interconnect delay = 6.284 ns ( 77.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.058 ns" { pause MSL[2]~88 MSL[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.058 ns" { pause {} pause~combout {} MSL[2]~88 {} MSL[2] {} } { 0.000ns 0.000ns 6.284ns 0.000ns } { 0.000ns 1.015ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.135 ns" { clk_odd clk_odd~clkctrl MSL[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.135 ns" { clk_odd {} clk_odd~combout {} clk_odd~clkctrl {} MSL[2] {} } { 0.000ns 0.000ns 0.251ns 1.058ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.058 ns" { pause MSL[2]~88 MSL[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.058 ns" { pause {} pause~combout {} MSL[2]~88 {} MSL[2] {} } { 0.000ns 0.000ns 6.284ns 0.000ns } { 0.000ns 1.015ns 0.651ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 30 14:19:10 2009 " "Info: Processing ended: Fri Jan 30 14:19:10 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}