📄 clock.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_odd10 register register count1\[0\] count1\[2\] 340.02 MHz Internal " "Info: Clock \"clk_odd10\" Internal fmax is restricted to 340.02 MHz between source register \"count1\[0\]\" and destination register \"count1\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.196 ns + Longest register register " "Info: + Longest register to register delay is 1.196 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count1\[0\] 1 REG LCFF_X24_Y14_N31 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y14_N31; Fanout = 12; REG Node = 'count1\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { count1[0] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.464 ns) + CELL(0.624 ns) 1.088 ns count1\[2\]~34 2 COMB LCCOMB_X24_Y14_N22 1 " "Info: 2: + IC(0.464 ns) + CELL(0.624 ns) = 1.088 ns; Loc. = LCCOMB_X24_Y14_N22; Fanout = 1; COMB Node = 'count1\[2\]~34'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.088 ns" { count1[0] count1[2]~34 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.196 ns count1\[2\] 3 REG LCFF_X24_Y14_N23 8 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.196 ns; Loc. = LCFF_X24_Y14_N23; Fanout = 8; REG Node = 'count1\[2\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { count1[2]~34 count1[2] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.732 ns ( 61.20 % ) " "Info: Total cell delay = 0.732 ns ( 61.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.464 ns ( 38.80 % ) " "Info: Total interconnect delay = 0.464 ns ( 38.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.196 ns" { count1[0] count1[2]~34 count1[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.196 ns" { count1[0] {} count1[2]~34 {} count1[2] {} } { 0.000ns 0.464ns 0.000ns } { 0.000ns 0.624ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_odd10 destination 3.171 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_odd10\" to destination register is 3.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.170 ns) 1.170 ns clk_odd10 1 CLK PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(1.170 ns) = 1.170 ns; Loc. = PIN_34; Fanout = 1; CLK Node = 'clk_odd10'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_odd10 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.427 ns clk_odd10~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.427 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk_odd10~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk_odd10 clk_odd10~clkctrl } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.666 ns) 3.171 ns count1\[2\] 3 REG LCFF_X24_Y14_N23 8 " "Info: 3: + IC(1.078 ns) + CELL(0.666 ns) = 3.171 ns; Loc. = LCFF_X24_Y14_N23; Fanout = 8; REG Node = 'count1\[2\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.744 ns" { clk_odd10~clkctrl count1[2] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.836 ns ( 57.90 % ) " "Info: Total cell delay = 1.836 ns ( 57.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.335 ns ( 42.10 % ) " "Info: Total interconnect delay = 1.335 ns ( 42.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.171 ns" { clk_odd10 clk_odd10~clkctrl count1[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.171 ns" { clk_odd10 {} clk_odd10~combout {} clk_odd10~clkctrl {} count1[2] {} } { 0.000ns 0.000ns 0.257ns 1.078ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_odd10 source 3.171 ns - Longest register " "Info: - Longest clock path from clock \"clk_odd10\" to source register is 3.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.170 ns) 1.170 ns clk_odd10 1 CLK PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(1.170 ns) = 1.170 ns; Loc. = PIN_34; Fanout = 1; CLK Node = 'clk_odd10'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_odd10 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.427 ns clk_odd10~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.427 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk_odd10~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk_odd10 clk_odd10~clkctrl } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.666 ns) 3.171 ns count1\[0\] 3 REG LCFF_X24_Y14_N31 12 " "Info: 3: + IC(1.078 ns) + CELL(0.666 ns) = 3.171 ns; Loc. = LCFF_X24_Y14_N31; Fanout = 12; REG Node = 'count1\[0\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.744 ns" { clk_odd10~clkctrl count1[0] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.836 ns ( 57.90 % ) " "Info: Total cell delay = 1.836 ns ( 57.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.335 ns ( 42.10 % ) " "Info: Total interconnect delay = 1.335 ns ( 42.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.171 ns" { clk_odd10 clk_odd10~clkctrl count1[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.171 ns" { clk_odd10 {} clk_odd10~combout {} clk_odd10~clkctrl {} count1[0] {} } { 0.000ns 0.000ns 0.257ns 1.078ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.171 ns" { clk_odd10 clk_odd10~clkctrl count1[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.171 ns" { clk_odd10 {} clk_odd10~combout {} clk_odd10~clkctrl {} count1[2] {} } { 0.000ns 0.000ns 0.257ns 1.078ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.171 ns" { clk_odd10 clk_odd10~clkctrl count1[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.171 ns" { clk_odd10 {} clk_odd10~combout {} clk_odd10~clkctrl {} count1[0] {} } { 0.000ns 0.000ns 0.257ns 1.078ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 78 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 78 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.196 ns" { count1[0] count1[2]~34 count1[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.196 ns" { count1[0] {} count1[2]~34 {} count1[2] {} } { 0.000ns 0.464ns 0.000ns } { 0.000ns 0.624ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.171 ns" { clk_odd10 clk_odd10~clkctrl count1[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.171 ns" { clk_odd10 {} clk_odd10~combout {} clk_odd10~clkctrl {} count1[2] {} } { 0.000ns 0.000ns 0.257ns 1.078ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.171 ns" { clk_odd10 clk_odd10~clkctrl count1[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.171 ns" { clk_odd10 {} clk_odd10~combout {} clk_odd10~clkctrl {} count1[0] {} } { 0.000ns 0.000ns 0.257ns 1.078ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { count1[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { count1[2] {} } { } { } "" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 78 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "MSH\[3\] pause clk_odd 5.690 ns register " "Info: tsu for register \"MSH\[3\]\" (data pin = \"pause\", clock pin = \"clk_odd\") is 5.690 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.865 ns + Longest pin register " "Info: + Longest pin to register delay is 8.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.015 ns) 1.015 ns pause 1 PIN PIN_39 6 " "Info: 1: + IC(0.000 ns) + CELL(1.015 ns) = 1.015 ns; Loc. = PIN_39; Fanout = 6; PIN Node = 'pause'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pause } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.251 ns) + CELL(0.202 ns) 7.468 ns MSH\[0\]~356 2 COMB LCCOMB_X24_Y12_N14 4 " "Info: 2: + IC(6.251 ns) + CELL(0.202 ns) = 7.468 ns; Loc. = LCCOMB_X24_Y12_N14; Fanout = 4; COMB Node = 'MSH\[0\]~356'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.453 ns" { pause MSH[0]~356 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.855 ns) 8.865 ns MSH\[3\] 3 REG LCFF_X23_Y12_N3 4 " "Info: 3: + IC(0.542 ns) + CELL(0.855 ns) = 8.865 ns; Loc. = LCFF_X23_Y12_N3; Fanout = 4; REG Node = 'MSH\[3\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.397 ns" { MSH[0]~356 MSH[3] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.072 ns ( 23.37 % ) " "Info: Total cell delay = 2.072 ns ( 23.37 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.793 ns ( 76.63 % ) " "Info: Total interconnect delay = 6.793 ns ( 76.63 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.865 ns" { pause MSH[0]~356 MSH[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.865 ns" { pause {} pause~combout {} MSH[0]~356 {} MSH[3] {} } { 0.000ns 0.000ns 6.251ns 0.542ns } { 0.000ns 1.015ns 0.202ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 29 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_odd destination 3.135 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_odd\" to destination register is 3.135 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.160 ns) 1.160 ns clk_odd 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.160 ns) = 1.160 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk_odd'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_odd } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.000 ns) 1.411 ns clk_odd~clkctrl 2 COMB CLKCTRL_G15 8 " "Info: 2: + IC(0.251 ns) + CELL(0.000 ns) = 1.411 ns; Loc. = CLKCTRL_G15; Fanout = 8; COMB Node = 'clk_odd~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.251 ns" { clk_odd clk_odd~clkctrl } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.058 ns) + CELL(0.666 ns) 3.135 ns MSH\[3\] 3 REG LCFF_X23_Y12_N3 4 " "Info: 3: + IC(1.058 ns) + CELL(0.666 ns) = 3.135 ns; Loc. = LCFF_X23_Y12_N3; Fanout = 4; REG Node = 'MSH\[3\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.724 ns" { clk_odd~clkctrl MSH[3] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.826 ns ( 58.25 % ) " "Info: Total cell delay = 1.826 ns ( 58.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.309 ns ( 41.75 % ) " "Info: Total interconnect delay = 1.309 ns ( 41.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.135 ns" { clk_odd clk_odd~clkctrl MSH[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.135 ns" { clk_odd {} clk_odd~combout {} clk_odd~clkctrl {} MSH[3] {} } { 0.000ns 0.000ns 0.251ns 1.058ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.865 ns" { pause MSH[0]~356 MSH[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.865 ns" { pause {} pause~combout {} MSH[0]~356 {} MSH[3] {} } { 0.000ns 0.000ns 6.251ns 0.542ns } { 0.000ns 1.015ns 0.202ns 0.855ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.135 ns" { clk_odd clk_odd~clkctrl MSH[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.135 ns" { clk_odd {} clk_odd~combout {} clk_odd~clkctrl {} MSH[3] {} } { 0.000ns 0.000ns 0.251ns 1.058ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_odd dataout\[2\] ML\[1\] 22.254 ns register " "Info: tco from clock \"clk_odd\" to destination pin \"dataout\[2\]\" through register \"ML\[1\]\" is 22.254 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_odd source 8.701 ns + Longest register " "Info: + Longest clock path from clock \"clk_odd\" to source register is 8.701 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.160 ns) 1.160 ns clk_odd 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.160 ns) = 1.160 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk_odd'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_odd } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.544 ns) + CELL(0.970 ns) 3.674 ns cn1 2 REG LCFF_X23_Y13_N15 3 " "Info: 2: + IC(1.544 ns) + CELL(0.970 ns) = 3.674 ns; Loc. = LCFF_X23_Y13_N15; Fanout = 3; REG Node = 'cn1'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.514 ns" { clk_odd cn1 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.628 ns) + CELL(0.970 ns) 5.272 ns cn2 3 REG LCFF_X24_Y13_N27 2 " "Info: 3: + IC(0.628 ns) + CELL(0.970 ns) = 5.272 ns; Loc. = LCFF_X24_Y13_N27; Fanout = 2; REG Node = 'cn2'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { cn1 cn2 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.696 ns) + CELL(0.000 ns) 6.968 ns cn2~clkctrl 4 COMB CLKCTRL_G11 8 " "Info: 4: + IC(1.696 ns) + CELL(0.000 ns) = 6.968 ns; Loc. = CLKCTRL_G11; Fanout = 8; COMB Node = 'cn2~clkctrl'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.696 ns" { cn2 cn2~clkctrl } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.666 ns) 8.701 ns ML\[1\] 5 REG LCFF_X24_Y11_N9 5 " "Info: 5: + IC(1.067 ns) + CELL(0.666 ns) = 8.701 ns; Loc. = LCFF_X24_Y11_N9; Fanout = 5; REG Node = 'ML\[1\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.733 ns" { cn2~clkctrl ML[1] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.766 ns ( 43.28 % ) " "Info: Total cell delay = 3.766 ns ( 43.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.935 ns ( 56.72 % ) " "Info: Total interconnect delay = 4.935 ns ( 56.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.701 ns" { clk_odd cn1 cn2 cn2~clkctrl ML[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.701 ns" { clk_odd {} clk_odd~combout {} cn1 {} cn2 {} cn2~clkctrl {} ML[1] {} } { 0.000ns 0.000ns 1.544ns 0.628ns 1.696ns 1.067ns } { 0.000ns 1.160ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 63 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.249 ns + Longest register pin " "Info: + Longest register to pin delay is 13.249 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ML\[1\] 1 REG LCFF_X24_Y11_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y11_N9; Fanout = 5; REG Node = 'ML\[1\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ML[1] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.202 ns) + CELL(0.650 ns) 1.852 ns Mux2~176 2 COMB LCCOMB_X24_Y13_N0 1 " "Info: 2: + IC(1.202 ns) + CELL(0.650 ns) = 1.852 ns; Loc. = LCCOMB_X24_Y13_N0; Fanout = 1; COMB Node = 'Mux2~176'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.852 ns" { ML[1] Mux2~176 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.094 ns) + CELL(0.651 ns) 3.597 ns Mux2~177 3 COMB LCCOMB_X24_Y12_N6 1 " "Info: 3: + IC(1.094 ns) + CELL(0.651 ns) = 3.597 ns; Loc. = LCCOMB_X24_Y12_N6; Fanout = 1; COMB Node = 'Mux2~177'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.745 ns" { Mux2~176 Mux2~177 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.650 ns) 4.655 ns Mux2~178 4 COMB LCCOMB_X24_Y12_N0 7 " "Info: 4: + IC(0.408 ns) + CELL(0.650 ns) = 4.655 ns; Loc. = LCCOMB_X24_Y12_N0; Fanout = 7; COMB Node = 'Mux2~178'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.058 ns" { Mux2~177 Mux2~178 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.094 ns) + CELL(0.647 ns) 6.396 ns Decoder1~106 5 COMB LCCOMB_X21_Y13_N16 1 " "Info: 5: + IC(1.094 ns) + CELL(0.647 ns) = 6.396 ns; Loc. = LCCOMB_X21_Y13_N16; Fanout = 1; COMB Node = 'Decoder1~106'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.741 ns" { Mux2~178 Decoder1~106 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 92 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.557 ns) + CELL(3.296 ns) 13.249 ns dataout\[2\] 6 PIN PIN_200 0 " "Info: 6: + IC(3.557 ns) + CELL(3.296 ns) = 13.249 ns; Loc. = PIN_200; Fanout = 0; PIN Node = 'dataout\[2\]'" { } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { Decoder1~106 dataout[2] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.894 ns ( 44.49 % ) " "Info: Total cell delay = 5.894 ns ( 44.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.355 ns ( 55.51 % ) " "Info: Total interconnect delay = 7.355 ns ( 55.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.249 ns" { ML[1] Mux2~176 Mux2~177 Mux2~178 Decoder1~106 dataout[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.249 ns" { ML[1] {} Mux2~176 {} Mux2~177 {} Mux2~178 {} Decoder1~106 {} dataout[2] {} } { 0.000ns 1.202ns 1.094ns 0.408ns 1.094ns 3.557ns } { 0.000ns 0.650ns 0.651ns 0.650ns 0.647ns 3.296ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.701 ns" { clk_odd cn1 cn2 cn2~clkctrl ML[1] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.701 ns" { clk_odd {} clk_odd~combout {} cn1 {} cn2 {} cn2~clkctrl {} ML[1] {} } { 0.000ns 0.000ns 1.544ns 0.628ns 1.696ns 1.067ns } { 0.000ns 1.160ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.249 ns" { ML[1] Mux2~176 Mux2~177 Mux2~178 Decoder1~106 dataout[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.249 ns" { ML[1] {} Mux2~176 {} Mux2~177 {} Mux2~178 {} Decoder1~106 {} dataout[2] {} } { 0.000ns 1.202ns 1.094ns 0.408ns 1.094ns 3.557ns } { 0.000ns 0.650ns 0.651ns 0.650ns 0.647ns 3.296ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
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