clock.tan.qmsg

用verilog实现的数字跑表

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_odd " "Info: Assuming node \"clk_odd\" is an undefined clock" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_odd" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_odd10 " "Info: Assuming node \"clk_odd10\" is an undefined clock" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_odd10" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cn2 " "Info: Detected ripple clock \"cn2\" as buffer" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "cn2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cn1 " "Info: Detected ripple clock \"cn1\" as buffer" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "cn1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_odd register SH\[3\] register cn2 180.47 MHz 5.541 ns Internal " "Info: Clock \"clk_odd\" has Internal fmax of 180.47 MHz between source register \"SH\[3\]\" and destination register \"cn2\" (period= 5.541 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.660 ns + Longest register register " "Info: + Longest register to register delay is 2.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SH\[3\] 1 REG LCFF_X24_Y13_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y13_N9; Fanout = 5; REG Node = 'SH\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { SH[3] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.485 ns) + CELL(0.499 ns) 1.984 ns Equal3~95 2 COMB LCCOMB_X24_Y13_N6 1 " "Info: 2: + IC(1.485 ns) + CELL(0.499 ns) = 1.984 ns; Loc. = LCCOMB_X24_Y13_N6; Fanout = 1; COMB Node = 'Equal3~95'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.984 ns" { SH[3] Equal3~95 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 2.552 ns cn2~44 3 COMB LCCOMB_X24_Y13_N26 1 " "Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 2.552 ns; Loc. = LCCOMB_X24_Y13_N26; Fanout = 1; COMB Node = 'cn2~44'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { Equal3~95 cn2~44 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.660 ns cn2 4 REG LCFF_X24_Y13_N27 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.660 ns; Loc. = LCFF_X24_Y13_N27; Fanout = 2; REG Node = 'cn2'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { cn2~44 cn2 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.813 ns ( 30.56 % ) " "Info: Total cell delay = 0.813 ns ( 30.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.847 ns ( 69.44 % ) " "Info: Total interconnect delay = 1.847 ns ( 69.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.660 ns" { SH[3] Equal3~95 cn2~44 cn2 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.660 ns" { SH[3] {} Equal3~95 {} cn2~44 {} cn2 {} } { 0.000ns 1.485ns 0.362ns 0.000ns } { 0.000ns 0.499ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.617 ns - Smallest " "Info: - Smallest clock skew is -2.617 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_odd destination 4.968 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_odd\" to destination register is 4.968 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.160 ns) 1.160 ns clk_odd 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.160 ns) = 1.160 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk_odd'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_odd } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.544 ns) + CELL(0.970 ns) 3.674 ns cn1 2 REG LCFF_X23_Y13_N15 3 " "Info: 2: + IC(1.544 ns) + CELL(0.970 ns) = 3.674 ns; Loc. = LCFF_X23_Y13_N15; Fanout = 3; REG Node = 'cn1'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.514 ns" { clk_odd cn1 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.628 ns) + CELL(0.666 ns) 4.968 ns cn2 3 REG LCFF_X24_Y13_N27 2 " "Info: 3: + IC(0.628 ns) + CELL(0.666 ns) = 4.968 ns; Loc. = LCFF_X24_Y13_N27; Fanout = 2; REG Node = 'cn2'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.294 ns" { cn1 cn2 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.796 ns ( 56.28 % ) " "Info: Total cell delay = 2.796 ns ( 56.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.172 ns ( 43.72 % ) " "Info: Total interconnect delay = 2.172 ns ( 43.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_odd cn1 cn2 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.968 ns" { clk_odd {} clk_odd~combout {} cn1 {} cn2 {} } { 0.000ns 0.000ns 1.544ns 0.628ns } { 0.000ns 1.160ns 0.970ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_odd source 7.585 ns - Longest register " "Info: - Longest clock path from clock \"clk_odd\" to source register is 7.585 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.160 ns) 1.160 ns clk_odd 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.160 ns) = 1.160 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk_odd'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_odd } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.544 ns) + CELL(0.970 ns) 3.674 ns cn1 2 REG LCFF_X23_Y13_N15 3 " "Info: 2: + IC(1.544 ns) + CELL(0.970 ns) = 3.674 ns; Loc. = LCFF_X23_Y13_N15; Fanout = 3; REG Node = 'cn1'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.514 ns" { clk_odd cn1 } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.166 ns) + CELL(0.000 ns) 5.840 ns cn1~clkctrl 3 COMB CLKCTRL_G2 8 " "Info: 3: + IC(2.166 ns) + CELL(0.000 ns) = 5.840 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'cn1~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.166 ns" { cn1 cn1~clkctrl } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.666 ns) 7.585 ns SH\[3\] 4 REG LCFF_X24_Y13_N9 5 " "Info: 4: + IC(1.079 ns) + CELL(0.666 ns) = 7.585 ns; Loc. = LCFF_X24_Y13_N9; Fanout = 5; REG Node = 'SH\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.745 ns" { cn1~clkctrl SH[3] } "NODE_NAME" } } { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.796 ns ( 36.86 % ) " "Info: Total cell delay = 2.796 ns ( 36.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.789 ns ( 63.14 % ) " "Info: Total interconnect delay = 4.789 ns ( 63.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.585 ns" { clk_odd cn1 cn1~clkctrl SH[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.585 ns" { clk_odd {} clk_odd~combout {} cn1 {} cn1~clkctrl {} SH[3] {} } { 0.000ns 0.000ns 1.544ns 2.166ns 1.079ns } { 0.000ns 1.160ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_odd cn1 cn2 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.968 ns" { clk_odd {} clk_odd~combout {} cn1 {} cn2 {} } { 0.000ns 0.000ns 1.544ns 0.628ns } { 0.000ns 1.160ns 0.970ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.585 ns" { clk_odd cn1 cn1~clkctrl SH[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.585 ns" { clk_odd {} clk_odd~combout {} cn1 {} cn1~clkctrl {} SH[3] {} } { 0.000ns 0.000ns 1.544ns 2.166ns 1.079ns } { 0.000ns 1.160ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.660 ns" { SH[3] Equal3~95 cn2~44 cn2 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.660 ns" { SH[3] {} Equal3~95 {} cn2~44 {} cn2 {} } { 0.000ns 1.485ns 0.362ns 0.000ns } { 0.000ns 0.499ns 0.206ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.968 ns" { clk_odd cn1 cn2 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.968 ns" { clk_odd {} clk_odd~combout {} cn1 {} cn2 {} } { 0.000ns 0.000ns 1.544ns 0.628ns } { 0.000ns 1.160ns 0.970ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.585 ns" { clk_odd cn1 cn1~clkctrl SH[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.585 ns" { clk_odd {} clk_odd~combout {} cn1 {} cn1~clkctrl {} SH[3] {} } { 0.000ns 0.000ns 1.544ns 2.166ns 1.079ns } { 0.000ns 1.160ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}