clock.sim.rpt

用verilog实现的数字跑表

; |clockdivisor|count[8]  ; |clockdivisor|count[8]  ; regout           ;
; |clockdivisor|clk       ; |clockdivisor|clk       ; out              ;
; |clockdivisor|clk1      ; |clockdivisor|clk1      ; pin_out          ;
; |clockdivisor|Add0~80   ; |clockdivisor|Add0~80   ; out0             ;
; |clockdivisor|Add0~81   ; |clockdivisor|Add0~81   ; out0             ;
; |clockdivisor|Add0~82   ; |clockdivisor|Add0~82   ; out0             ;
; |clockdivisor|Add0~83   ; |clockdivisor|Add0~83   ; out0             ;
; |clockdivisor|Add0~84   ; |clockdivisor|Add0~84   ; out0             ;
; |clockdivisor|Add0~85   ; |clockdivisor|Add0~85   ; out0             ;
; |clockdivisor|Add0~86   ; |clockdivisor|Add0~86   ; out0             ;
; |clockdivisor|Add0~87   ; |clockdivisor|Add0~87   ; out0             ;
; |clockdivisor|Add0~88   ; |clockdivisor|Add0~88   ; out0             ;
; |clockdivisor|Add0~89   ; |clockdivisor|Add0~89   ; out0             ;
; |clockdivisor|Add0~90   ; |clockdivisor|Add0~90   ; out0             ;
; |clockdivisor|Add0~91   ; |clockdivisor|Add0~91   ; out0             ;
; |clockdivisor|Add0~92   ; |clockdivisor|Add0~92   ; out0             ;
; |clockdivisor|Add0~93   ; |clockdivisor|Add0~93   ; out0             ;
; |clockdivisor|Add0~94   ; |clockdivisor|Add0~94   ; out0             ;
; |clockdivisor|Equal0~33 ; |clockdivisor|Equal0~33 ; out0             ;
+-------------------------+-------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------+
; Missing 1-Value Coverage                                             ;
+-------------------------+-------------------------+------------------+
; Node Name               ; Output Port Name        ; Output Port Type ;
+-------------------------+-------------------------+------------------+
; |clockdivisor|count~0   ; |clockdivisor|count~0   ; out              ;
; |clockdivisor|count~1   ; |clockdivisor|count~1   ; out              ;
; |clockdivisor|count~2   ; |clockdivisor|count~2   ; out              ;
; |clockdivisor|count~3   ; |clockdivisor|count~3   ; out              ;
; |clockdivisor|count~4   ; |clockdivisor|count~4   ; out              ;
; |clockdivisor|count~5   ; |clockdivisor|count~5   ; out              ;
; |clockdivisor|count~6   ; |clockdivisor|count~6   ; out              ;
; |clockdivisor|count~16  ; |clockdivisor|count~16  ; out              ;
; |clockdivisor|count~17  ; |clockdivisor|count~17  ; out              ;
; |clockdivisor|count~18  ; |clockdivisor|count~18  ; out              ;
; |clockdivisor|count~19  ; |clockdivisor|count~19  ; out              ;
; |clockdivisor|count~20  ; |clockdivisor|count~20  ; out              ;
; |clockdivisor|count~21  ; |clockdivisor|count~21  ; out              ;
; |clockdivisor|count~22  ; |clockdivisor|count~22  ; out              ;
; |clockdivisor|count[9]  ; |clockdivisor|count[9]  ; regout           ;
; |clockdivisor|count[10] ; |clockdivisor|count[10] ; regout           ;
; |clockdivisor|count[11] ; |clockdivisor|count[11] ; regout           ;
; |clockdivisor|count[12] ; |clockdivisor|count[12] ; regout           ;
; |clockdivisor|count[13] ; |clockdivisor|count[13] ; regout           ;
; |clockdivisor|count[14] ; |clockdivisor|count[14] ; regout           ;
; |clockdivisor|count[15] ; |clockdivisor|count[15] ; regout           ;
; |clockdivisor|reset_n   ; |clockdivisor|reset_n   ; out              ;
; |clockdivisor|Add0~95   ; |clockdivisor|Add0~95   ; out0             ;
; |clockdivisor|Add0~96   ; |clockdivisor|Add0~96   ; out0             ;
; |clockdivisor|Add0~97   ; |clockdivisor|Add0~97   ; out0             ;
; |clockdivisor|Add0~98   ; |clockdivisor|Add0~98   ; out0             ;
; |clockdivisor|Add0~99   ; |clockdivisor|Add0~99   ; out0             ;
; |clockdivisor|Add0~100  ; |clockdivisor|Add0~100  ; out0             ;
; |clockdivisor|Add0~101  ; |clockdivisor|Add0~101  ; out0             ;
; |clockdivisor|Add0~102  ; |clockdivisor|Add0~102  ; out0             ;
; |clockdivisor|Add0~103  ; |clockdivisor|Add0~103  ; out0             ;
; |clockdivisor|Add0~104  ; |clockdivisor|Add0~104  ; out0             ;
; |clockdivisor|Add0~105  ; |clockdivisor|Add0~105  ; out0             ;
; |clockdivisor|Add0~106  ; |clockdivisor|Add0~106  ; out0             ;
; |clockdivisor|Add0~107  ; |clockdivisor|Add0~107  ; out0             ;
; |clockdivisor|Add0~108  ; |clockdivisor|Add0~108  ; out0             ;
+-------------------------+-------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------+
; Missing 0-Value Coverage                                             ;
+-------------------------+-------------------------+------------------+
; Node Name               ; Output Port Name        ; Output Port Type ;
+-------------------------+-------------------------+------------------+
; |clockdivisor|count~0   ; |clockdivisor|count~0   ; out              ;
; |clockdivisor|count~1   ; |clockdivisor|count~1   ; out              ;
; |clockdivisor|count~2   ; |clockdivisor|count~2   ; out              ;
; |clockdivisor|count~3   ; |clockdivisor|count~3   ; out              ;
; |clockdivisor|count~4   ; |clockdivisor|count~4   ; out              ;
; |clockdivisor|count~5   ; |clockdivisor|count~5   ; out              ;
; |clockdivisor|count~6   ; |clockdivisor|count~6   ; out              ;
; |clockdivisor|count~16  ; |clockdivisor|count~16  ; out              ;
; |clockdivisor|count~17  ; |clockdivisor|count~17  ; out              ;
; |clockdivisor|count~18  ; |clockdivisor|count~18  ; out              ;
; |clockdivisor|count~19  ; |clockdivisor|count~19  ; out              ;
; |clockdivisor|count~20  ; |clockdivisor|count~20  ; out              ;
; |clockdivisor|count~21  ; |clockdivisor|count~21  ; out              ;
; |clockdivisor|count~22  ; |clockdivisor|count~22  ; out              ;
; |clockdivisor|count[9]  ; |clockdivisor|count[9]  ; regout           ;
; |clockdivisor|count[10] ; |clockdivisor|count[10] ; regout           ;
; |clockdivisor|count[11] ; |clockdivisor|count[11] ; regout           ;
; |clockdivisor|count[12] ; |clockdivisor|count[12] ; regout           ;
; |clockdivisor|count[13] ; |clockdivisor|count[13] ; regout           ;
; |clockdivisor|count[14] ; |clockdivisor|count[14] ; regout           ;
; |clockdivisor|count[15] ; |clockdivisor|count[15] ; regout           ;
; |clockdivisor|reset_n   ; |clockdivisor|reset_n   ; out              ;
; |clockdivisor|Add0~95   ; |clockdivisor|Add0~95   ; out0             ;
; |clockdivisor|Add0~96   ; |clockdivisor|Add0~96   ; out0             ;
; |clockdivisor|Add0~97   ; |clockdivisor|Add0~97   ; out0             ;
; |clockdivisor|Add0~98   ; |clockdivisor|Add0~98   ; out0             ;
; |clockdivisor|Add0~99   ; |clockdivisor|Add0~99   ; out0             ;
; |clockdivisor|Add0~100  ; |clockdivisor|Add0~100  ; out0             ;
; |clockdivisor|Add0~101  ; |clockdivisor|Add0~101  ; out0             ;
; |clockdivisor|Add0~102  ; |clockdivisor|Add0~102  ; out0             ;
; |clockdivisor|Add0~103  ; |clockdivisor|Add0~103  ; out0             ;
; |clockdivisor|Add0~104  ; |clockdivisor|Add0~104  ; out0             ;
; |clockdivisor|Add0~105  ; |clockdivisor|Add0~105  ; out0             ;
; |clockdivisor|Add0~106  ; |clockdivisor|Add0~106  ; out0             ;
; |clockdivisor|Add0~107  ; |clockdivisor|Add0~107  ; out0             ;
; |clockdivisor|Add0~108  ; |clockdivisor|Add0~108  ; out0             ;
+-------------------------+-------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Jan 27 23:02:14 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off clock -c clock
Info: Using vector source file "F:/work/project/clock/clock.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      57.14 %
Info: Number of transitions in simulation is 124725
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 97 megabytes of memory during processing
    Info: Processing ended: Tue Jan 27 23:02:15 2009
    Info: Elapsed time: 00:00:01