csa_1weight_odd.vhd

是Nios II處理器下客製化指令的一個32位元浮點數除法器

-- hds header_start
--
-- VHDL Architecture FPdivider24.csa_1weight_odd.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 16:32:58 2003/11/26
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;



entity csa_1weight_odd is
port(
     a:in std_logic;
     b:in std_logic;
     c:in std_logic;
     d:in std_logic;
     e:in std_logic;
     f:in std_logic;
     g:in std_logic;
     h:in std_logic;
     
    cin_0:in std_logic;
    cin_1:in std_logic;
    cin_2:in std_logic;
    cin_3:in std_logic;  
    cin_4:in std_logic;
    cin_5:in std_logic;   

    cout_0:out std_logic;
    cout_1:out std_logic;
    cout_2:out std_logic;
    cout_3:out std_logic;
    cout_4:out std_logic;
    cout_5:out std_logic;
    cout_6:out std_logic;
    
    sum:out std_logic);

end csa_1weight_odd;

architecture arch of csa_1weight_odd is

component csa_1bit
    port(
         a:in std_logic;
         b:in std_logic;
         c:in std_logic;
       sum:out std_logic;
      carry:out std_logic);
end component;
 
signal zero:std_logic:='0';
signal u00_s:std_logic;
signal u01_s:std_logic;
signal u02_s:std_logic;

signal u10_s:std_logic;
signal u11_s:std_logic;

signal u20_s:std_logic;
--signal u30_s:std_logic;


begin

--row 0  begin----------------------
u00:csa_1bit port map(
        a=>a,
         b=>b,
         c=>c,
       sum=>u00_s,
      carry=>cout_0);

u01:csa_1bit port map(
        a=>d,
         b=>e,
         c=>f,
       sum=>u01_s,
      carry=>cout_1);

u02:csa_1bit port map(
        a=>g,
         b=>h,
         c=>zero,
       sum=>u02_s,
      carry=>cout_2);


--row 1 begin------------------------
u10:csa_1bit port map(
        a=>cin_0,
         b=>cin_1,
         c=>u00_s,
       sum=>u10_s,
      carry=>cout_3);

u11:csa_1bit port map(
        a=>cin_2,
         b=>u01_s,
         c=>u02_s,
       sum=>u11_s,
      carry=>cout_4);

--row 2 begin-------------------------
u20:csa_1bit port map(
        a=>cin_3,
         b=>cin_4,
         c=>u10_s,
       sum=>u20_s,
      carry=>cout_5);

--row 3 begin-----------------------
u30:csa_1bit port map(
        a=>cin_5,
         b=>u20_s,
         c=>u11_s,
       sum=>sum,
      carry=>cout_6);
end arch;