csa_1bit.vhd

来自「是Nios II處理器下客製化指令的一個32位元浮點數除法器」· VHDL 代码 · 共 80 行

-- hds header_start
--
-- VHDL Architecture FPdivider24.csa_1bit.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 16:04:58 2003/11/26
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end




LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

entity csa_1bit is
port(
     a,b,c:in std_logic;
     sum,carry:out std_logic);
end csa_1bit;


ARCHITECTURE tbl OF csa_1bit IS

signal S:std_logic_vector(2 downto 0);

begin
S<=a & b & c;

process(s)
begin


case S is
   when "000"=>
               sum<='0'; 
             carry<='0';

   when "001"=>
               sum<='1';
             carry<='0';

   when "010"=>
               sum<='1'; 
             carry<='0';

   when "011"=>
               sum<='0'; 
             carry<='1';

   when "100"=>
               sum<='1';
             carry<='0';

   when "101"=>
               sum<='0'; 
             carry<='1';   

   when "110"=>
               sum<='0'; 
             carry<='1';

   when others=>
               sum<='1';
             carry<='1';

end case;
end process;
  
END tbl;