sum28.vhd

是Nios II處理器下客製化指令的一個32位元浮點數除法器

-- hds header_start
--
-- VHDL Architecture FPdivider24.sum28.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 14:11:27 2003/12/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY sum28 IS
   PORT( 
      in_1bx  : IN     std_logic_vector (20 DOWNTO 0);
      in_1bx2 : IN     std_logic_vector (16 DOWNTO 0);
      in_1bx3 : IN     std_logic_vector (11 DOWNTO 0);
      sout    : OUT    std_logic_vector (29 DOWNTO 0)
   );

-- Declarations

END sum28 ;

-- hds interface_end
ARCHITECTURE untitled OF sum28 IS
signal a:std_logic_vector(29 downto 0);
signal b:std_logic_vector(29 downto 0);
signal c:std_logic_vector(29 downto 0);
signal temps:std_logic_vector(29 downto 0);
BEGIN
a<="000000" & in_1bx &"000";
b<="000000000000" & in_1bx2 &'0';
c<="000000000000000000" & in_1bx3;

temps(29 downto 0)<=unsigned(a)+unsigned(b)+unsigned(c);
sout(29)<='1';
sout(28 downto 0)<=temps(29 downto 1);
END untitled;