mult_final28.vhd

来自「是Nios II處理器下客製化指令的一個32位元浮點數除法器」· VHDL 代码 · 共 35 行

-- hds header_start
--
-- VHDL Architecture FPdivider24.mult_final28.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 16:31:33 2003/12/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mult_final28 IS
   PORT( 
      in_ax          : IN     std_logic_vector (29 DOWNTO 0);
      in_s           : IN     std_logic_vector (29 DOWNTO 0);
      final_result24 : OUT    std_logic_vector (27 DOWNTO 0)
   );

-- Declarations

END mult_final28 ;

-- hds interface_end
ARCHITECTURE untitled OF mult_final28 IS
signal tmp56:std_logic_vector(59 downto 0);
BEGIN
tmp56<=unsigned(in_ax)*unsigned(in_s);
final_result24<=tmp56(58 downto 31);
END untitled;