square24.vhd

来自「是Nios II處理器下客製化指令的一個32位元浮點數除法器」· VHDL 代码 · 共 35 行

-- hds header_start
--
-- VHDL Architecture FPdivider24.square24.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 14:53:43 2003/11/29
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY square24 IS
   PORT( 
      a      : IN     std_logic_vector (23 DOWNTO 0);
      answer : OUT    std_logic_vector (47 DOWNTO 0)
   );

-- Declarations

END square24 ;

-- hds interface_end
ARCHITECTURE dw OF square24 IS
BEGIN

answer<=unsigned(a)*unsigned(a);

END dw;