📄 table_shell.vhd
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-- hds header_start
--
-- VHDL Entity FPmix32.table_shell.symbol
--
-- Created:
-- by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
-- at - 15:33:38 2004/03/23
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY table_shell IS
PORT(
inputb : IN std_logic_vector (23 DOWNTO 0);
X_value : OUT std_logic_vector (7 DOWNTO 0)
);
-- Declarations
END table_shell ;
-- hds interface_end
--
-- VHDL Architecture FPmix32.table_shell.struct
--
-- Created:
-- by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
-- at - 15:33:38 2004/03/23
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
--LIBRARY FPmix32;
ARCHITECTURE struct OF table_shell IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL L : std_logic_vector(6 DOWNTO 0);
SIGNAL M : std_logic_vector(6 DOWNTO 0);
-- Component Declarations
COMPONENT index
PORT (
inputb : IN std_logic_vector (23 DOWNTO 0);
L : OUT std_logic_vector (6 DOWNTO 0)
);
END COMPONENT;
COMPONENT table
PORT (
L : IN std_logic_vector (6 DOWNTO 0);
M : OUT std_logic_vector (6 DOWNTO 0)
);
END COMPONENT;
COMPONENT words
PORT (
M : IN std_logic_vector (6 DOWNTO 0);
X_value : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
-- FOR ALL : index USE ENTITY FPmix32.index;
-- FOR ALL : table USE ENTITY FPmix32.table;
-- FOR ALL : words USE ENTITY FPmix32.words;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
I1 : index
PORT MAP (
inputb => inputb,
L => L
);
I0 : table
PORT MAP (
L => L,
M => M
);
I2 : words
PORT MAP (
M => M,
X_value => X_value
);
END struct;
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