msub24_1bx_shell.vhd

是Nios II處理器下客製化指令的一個32位元浮點數除法器

-- hds header_start
--
-- VHDL Entity FPmix32.msub24_1bx_shell.symbol
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 15:38:38 2004/03/23
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY msub24_1bx_shell IS
   PORT( 
      in_X   : IN     std_logic_vector (7 DOWNTO 0);
      in_b   : IN     std_logic_vector (23 DOWNTO 0);
      result : OUT    std_logic_vector (23 DOWNTO 0)
   );

-- Declarations

END msub24_1bx_shell ;

-- hds interface_end
--
-- VHDL Architecture FPmix32.msub24_1bx_shell.struct
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 15:38:38 2004/03/23
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


--LIBRARY FPmix32;

ARCHITECTURE struct OF msub24_1bx_shell IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL a : std_logic_vector(23 DOWNTO 0);
   SIGNAL b : std_logic_vector(23 DOWNTO 0);
   SIGNAL c : std_logic_vector(23 DOWNTO 0);
   SIGNAL d : std_logic_vector(22 DOWNTO 0);
   SIGNAL e : std_logic_vector(21 DOWNTO 0);
   SIGNAL f : std_logic_vector(20 DOWNTO 0);
   SIGNAL g : std_logic_vector(19 DOWNTO 0);
   SIGNAL h : std_logic_vector(18 DOWNTO 0);
   SIGNAL i : std_logic;


   -- Component Declarations
   COMPONENT conv
   PORT (
      in_X : IN     std_logic_vector (7 DOWNTO 0);
      in_b : IN     std_logic_vector (23 DOWNTO 0);
      a    : OUT    std_logic_vector (23 DOWNTO 0);
      b    : OUT    std_logic_vector (23 DOWNTO 0);
      c    : OUT    std_logic_vector (23 DOWNTO 0);
      d    : OUT    std_logic_vector (22 DOWNTO 0);
      e    : OUT    std_logic_vector (21 DOWNTO 0);
      f    : OUT    std_logic_vector (20 DOWNTO 0);
      g    : OUT    std_logic_vector (19 DOWNTO 0);
      h    : OUT    std_logic_vector (18 DOWNTO 0);
      i    : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT mult_sub24_1bx
   PORT (
      a      : IN     std_logic_vector (23 DOWNTO 0);
      b      : IN     std_logic_vector (23 DOWNTO 0);
      c      : IN     std_logic_vector (23 DOWNTO 0);
      d      : IN     std_logic_vector (22 DOWNTO 0);
      e      : IN     std_logic_vector (21 DOWNTO 0);
      f      : IN     std_logic_vector (20 DOWNTO 0);
      g      : IN     std_logic_vector (19 DOWNTO 0);
      h      : IN     std_logic_vector (18 DOWNTO 0);
      i      : IN     std_logic ;
      result : OUT    std_logic_vector (23 DOWNTO 0)
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
--   FOR ALL : conv USE ENTITY FPmix32.conv;
--   FOR ALL : mult_sub24_1bx USE ENTITY FPmix32.mult_sub24_1bx;
   -- pragma synthesis_on


BEGIN
   -- Instance port mappings.
   I1 : conv
      PORT MAP (
         in_X => in_X,
         in_b => in_b,
         a    => a,
         b    => b,
         c    => c,
         d    => d,
         e    => e,
         f    => f,
         g    => g,
         h    => h,
         i    => i
      );
   I0 : mult_sub24_1bx
      PORT MAP (
         a      => a,
         b      => b,
         c      => c,
         d      => d,
         e      => e,
         f      => f,
         g      => g,
         h      => h,
         i      => i,
         result => result
      );

END struct;