📄 conv.vhd
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-- hds header_start
--
-- VHDL Architecture FPmix32.conv1.untitled
--
-- Created:
-- by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
-- at - 15:25:18 2004/02/07
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY conv IS
PORT(
in_X : IN std_logic_vector (7 DOWNTO 0);
in_b : IN std_logic_vector (23 DOWNTO 0);
a : OUT std_logic_vector (23 DOWNTO 0);
b : OUT std_logic_vector (23 DOWNTO 0);
c : OUT std_logic_vector (23 DOWNTO 0);
d : OUT std_logic_vector (22 DOWNTO 0);
e : OUT std_logic_vector (21 DOWNTO 0);
f : OUT std_logic_vector (20 DOWNTO 0);
g : OUT std_logic_vector (19 DOWNTO 0);
h : OUT std_logic_vector (18 DOWNTO 0);
i : OUT std_logic
);
-- Declarations
END conv ;
-- hds interface_end
ARCHITECTURE untitled OF conv IS
BEGIN
process(in_X,in_b)
begin
if(in_X(0)='1')then
a<= '1'¬ in_b(23 downto 1);
else
a<="000000000000000000000000";
end if;
if(in_X(1)='1')then
b<=not in_b;
c(0)<='1';
else
b<="000000000000000000000000";
c(0)<='0';
end if;
if(in_X(2)='1')then
c(23 downto 1)<=not in_b(22 downto 0);
d(0)<='1';
else
c(23 downto 1)<="00000000000000000000000";
d(0)<='0';
end if;
if(in_X(3)='1')then
d(22 downto 1)<=not in_b(21 downto 0);
e(0)<='1';
else
d(22 downto 1)<="0000000000000000000000";
e(0)<='0';
end if;
if(in_X(4)='1')then
e(21 downto 1)<=not in_b(20 downto 0);
f(0)<='1';
else
e(21 downto 1)<="000000000000000000000";
f(0)<='0';
end if;
if(in_X(5)='1')then
f(20 downto 1)<=not in_b(19 downto 0);
g(0)<='1';
else
f(20 downto 1)<="00000000000000000000";
g(0)<='0';
end if;
if(in_X(6)='1')then
g(19 downto 1)<=not in_b(18 downto 0);
h(0)<='1';
else
g(19 downto 1)<="0000000000000000000";
h(0)<='0';
end if;
if(in_X(7)='1')then
h(18 downto 1)<=not in_b(17 downto 0);
i<='1';
else
h(18 downto 1)<="000000000000000000";
i<='0';
end if;
end process;
END untitled;
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