mult_sub24_1bx.vhd

是Nios II處理器下客製化指令的一個32位元浮點數除法器

-- hds header_start
--
-- VHDL Architecture FPdivider24.mult_sub24_1bx.untitled
--
-- Created:
--          by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
--          at - 16:00:31 2003/11/26
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity mult_sub24_1bx is 
port(
     a:in std_logic_vector(23 downto 0);
     b:in std_logic_vector(23 downto 0);
     c:in std_logic_vector(23 downto 0);

     d:in std_logic_vector(22 downto 0);
     e:in std_logic_vector(21 downto 0);
     f:in std_logic_vector(20 downto 0);
     g:in std_logic_vector(19 downto 0);
     h:in std_logic_vector(18 downto 0);     
     i:in std_logic;
     result:out std_logic_vector(23 downto 0));

end mult_sub24_1bx;

architecture arch of mult_sub24_1bx is

component csa_1bit
    port(
         a:in std_logic;
         b:in std_logic;
         c:in std_logic;
       sum:out std_logic;
      carry:out std_logic);
end component;


component csa_2weight
    port(
       a:in std_logic_vector(1 downto 0);
       b:in std_logic_vector(1 downto 0);
       c:in std_logic_vector(1 downto 0);
       d:in std_logic_vector(1 downto 0);
       e:in std_logic_vector(1 downto 0);
       f:in std_logic_vector(1 downto 0);
       g:in std_logic_vector(1 downto 0);
       h:in std_logic_vector(1 downto 0);
     
       cin_0:in std_logic;
       cin_1:in std_logic;
       cin_2:in std_logic;
       cin_3:in std_logic;  
       cin_4:in std_logic;
       cin_5:in std_logic;   

       cout_0:out std_logic;
       cout_1:out std_logic;
       cout_2:out std_logic;
       cout_3:out std_logic;
       cout_4:out std_logic;
       cout_5:out std_logic;

       cout_to_cpa:out std_logic_vector(1 downto 0);
       sum_to_cpa:out std_logic_vector(1 downto 0));

end component;



component csa_1weight_odd
    port(
        a:in std_logic;
        b:in std_logic;
        c:in std_logic;
        d:in std_logic;
        e:in std_logic;
        f:in std_logic;
        g:in std_logic;
        h:in std_logic;
     
        cin_0:in std_logic;
        cin_1:in std_logic;
        cin_2:in std_logic;
        cin_3:in std_logic;  
        cin_4:in std_logic;
        cin_5:in std_logic;   

        cout_0:out std_logic;
        cout_1:out std_logic;
        cout_2:out std_logic;
        cout_3:out std_logic;
        cout_4:out std_logic;
        cout_5:out std_logic;
        cout_6:out std_logic;
        sum:out std_logic);
end component;



component rca_20bit
    --generic(length:integer:=7);
    port(
        x:in std_logic_vector(19 downto 0);
        y:in std_logic_vector(19 downto 0);
        s:out std_logic_vector(19 downto 0));

end component;



signal zero:std_logic:='0';
---row 0 signal-----------------
signal u00_s:std_logic;  --u00: the first 0 is row number, another is column number
signal u00_c:std_logic;

signal u01_s:std_logic;  
signal u01_c:std_logic;
 
signal u02_s:std_logic;  
signal u02_c:std_logic;

signal u03_s:std_logic;  
signal u03_c:std_logic; 

signal u04_s:std_logic;  
signal u04_c:std_logic;

signal u05_s:std_logic;  
signal u05_c:std_logic;

signal u06_s:std_logic;  
signal u06_c:std_logic;

signal u07_s:std_logic;  
signal u07_c:std_logic; 

signal u08_s:std_logic;  
signal u08_c:std_logic;

signal u09_s:std_logic;  
signal u09_c:std_logic; 

signal u010_s:std_logic;  
signal u010_c:std_logic;

signal u011_s:std_logic;  
signal u011_c:std_logic;

signal u012_s:std_logic;  
signal u012_c:std_logic;

signal u013_s:std_logic;  
signal u013_c:std_logic;


---row 1 signal--------------------------
signal u10_s:std_logic;  
signal u10_c:std_logic;

signal u11_s:std_logic;  
signal u11_c:std_logic;
 
signal u12_s:std_logic;  
signal u12_c:std_logic;

signal u13_s:std_logic;  
signal u13_c:std_logic; 

signal u14_s:std_logic;  
signal u14_c:std_logic;

signal u15_s:std_logic;  
signal u15_c:std_logic;

signal u16_s:std_logic;  
signal u16_c:std_logic;

signal u17_s:std_logic;  
signal u17_c:std_logic; 

signal u18_s:std_logic;  
signal u18_c:std_logic;



---row 2 signal----------------------------------
signal u20_s:std_logic;  
signal u20_c:std_logic;

signal u21_s:std_logic;  
signal u21_c:std_logic;
 
signal u22_s:std_logic;  
signal u22_c:std_logic;

signal u23_s:std_logic;  
signal u23_c:std_logic; 

signal u24_s:std_logic;  
signal u24_c:std_logic;


---row 3 signal------------
--also RCA input signal------
-----------------------------
signal u3_s:std_logic_vector(20 downto 0);
signal u3_c:std_logic_vector(20 downto 0);

--signal u30_s:std_logic;  
--signal u30_c:std_logic;

--signal u31_s:std_logic;  
--signal u31_c:std_logic;
 
--signal u32_s:std_logic;  
--signal u32_c:std_logic;

--signal u33_s:std_logic;  
--signal u33_c:std_logic; 

--signal u34_s:std_logic;  
--signal u34_c:std_logic;

--signal u35_s:std_logic;  
--signal u35_c:std_logic;

--signal u36_s:std_logic;  
--signal u36_c:std_logic;


--between component signal---
signal a_cout_0:std_logic_vector(7 downto 0);
signal a_cout_1:std_logic_vector(7 downto 0);
signal a_cout_2:std_logic_vector(7 downto 0);
signal a_cout_3:std_logic_vector(7 downto 0);
signal a_cout_4:std_logic_vector(7 downto 0);
signal a_cout_5:std_logic_vector(7 downto 0);

--signal a0_cout_0:std_logic;
--signal a0_cout_1:std_logic;
--signal a0_cout_2:std_logic;
--signal a0_cout_3:std_logic;
--signal a0_cout_4:std_logic;
--signal a0_cout_5:std_logic;

signal final_cout_0:std_logic;
signal final_cout_1:std_logic;
signal final_cout_2:std_logic;
signal final_cout_3:std_logic;
signal final_cout_4:std_logic;
signal final_cout_5:std_logic;    


begin
--2^0 beign----------------------2^0 weight's CSA adder 
u00:csa_1bit port map(
                    a=>a(0),
                    b=>b(0),
                    c=>c(0),
                  sum=>u00_s,
                carry=>u00_c);

--2^1 begin------------------------
u01:csa_1bit port map(
                    a=>a(1),
                    b=>b(1),
                    c=>c(1),
                  sum=>u01_s,
                carry=>u01_c);

--row1
u10:csa_1bit port map(
                    a=>u00_c,
                    b=>u01_s,
                    c=>d(0),   ----d(0)='1'
                  sum=>u10_s,
                carry=>u10_c);



--2^2 begin-------------------------
u02:csa_1bit port map(
                    a=>a(2),
                    b=>b(2),
                    c=>c(2),
                  sum=>u02_s,
                carry=>u02_c);

u03:csa_1bit port map(
                    a=>d(1),
                    b=>e(0),
                    c=>zero,   ----zero value
                  sum=>u03_s,
                carry=>u03_c);
--row1
u11:csa_1bit port map(
                    a=>u01_c,
                    b=>u02_s,
                    c=>u03_s,   
                  sum=>u11_s,
                carry=>u11_c);
--row2
u20:csa_1bit port map(
                    a=>u10_c,
                    b=>u11_s,
                    c=>zero,   --zero value
                  sum=>u20_s,
                carry=>u20_c);

--2^3 begin--------------------------
u04:csa_1bit port map(
                    a=>a(3),
                    b=>b(3),
                    c=>c(3),
                  sum=>u04_s,
                carry=>u04_c);

u05:csa_1bit port map(
                    a=>d(2),
                    b=>e(1),
                    c=>f(0),
                  sum=>u05_s,
                carry=>u05_c);
--row1
u12:csa_1bit port map(
                    a=>u02_c,
                    b=>u03_c,
                    c=>u04_s,   
                  sum=>u12_s,
                carry=>u12_c);

--row2
u21:csa_1bit port map(
                    a=>u11_c,
                    b=>u12_s,
                    c=>u05_s,   
                  sum=>u21_s,
                carry=>u21_c);

--row3
u30:csa_1bit port map(
                    a=>u20_c,
                    b=>u21_s,
                    c=>zero,   --zero value
                  sum=>u3_s(0),
                carry=>u3_c(0));



--2^4 begin-------------------------
u06:csa_1bit port map(
                    a=>a(4),
                    b=>b(4),
                    c=>c(4),
                  sum=>u06_s,
                carry=>u06_c);

u07:csa_1bit port map(
                    a=>d(3),
                    b=>e(2),
                    c=>f(1),
                  sum=>u07_s,
                carry=>u07_c);

--row1
u13:csa_1bit port map(
                    a=>u04_c,
                    b=>u06_s,
                    c=>u07_s,   
                  sum=>u13_s,
                carry=>u13_c);

u14:csa_1bit port map(
                    a=>u05_c,
                    b=>g(0),  ---g(0)='1'
                    c=>zero,   ----zero value
                  sum=>u14_s,
                carry=>u14_c);

--row2
u22:csa_1bit port map(
                    a=>u12_c,
                    b=>u13_s,
                    c=>u14_s,   
                  sum=>u22_s,
                carry=>u22_c);

--row3
u31:csa_1bit port map(
                    a=>u21_c,
                    b=>u22_s,
                    c=>zero,  ---zero value 
                  sum=>u3_s(1),
                carry=>u3_c(1));


--2^5 begin------------------------
u08:csa_1bit port map(
                    a=>a(5),
                    b=>b(5),
                    c=>c(5),
                  sum=>u08_s,
                carry=>u08_c);

u09:csa_1bit port map(
                    a=>d(4),
                    b=>e(3),
                    c=>f(2),
                  sum=>u09_s,
                carry=>u09_c);

u010:csa_1bit port map(
                    a=>g(1),
                    b=>h(0),
                    c=>zero,   ---zero value
                  sum=>u010_s,
                carry=>u010_c);

--row1
u15:csa_1bit port map(
                    a=>u06_c,
                    b=>u07_c,
                    c=>u08_s,
                  sum=>u15_s,
                carry=>u15_c);

u16:csa_1bit port map(
                    a=>zero,
                    b=>u09_s,
                    c=>u010_s,
                  sum=>u16_s,
                carry=>u16_c);

--row2
u23:csa_1bit port map(
                    a=>u13_c,
                    b=>u14_c,
                    c=>u15_s,   
                  sum=>u23_s,
                carry=>u23_c);

--row3
u32:csa_1bit port map(
                    a=>u22_c,
                    b=>u23_s,
                    c=>u16_s,   
                  sum=>u3_s(2),
                carry=>u3_c(2));


--2^6 begin-------------------
u011:csa_1bit port map(
                    a=>a(6),
                    b=>b(6),
                    c=>c(6),
                  sum=>u011_s,
                carry=>u011_c);

u012:csa_1bit port map(
                    a=>d(5),
                    b=>e(4),
                    c=>f(3),
                  sum=>u012_s,
                carry=>u012_c);

u013:csa_1bit port map(
                    a=>g(2),
                    b=>h(1),
                    c=>i,
                  sum=>u013_s,
                carry=>u013_c);


--row1
u17:csa_1bit port map(
                    a=>u08_c,
                    b=>u011_s,
                    c=>u012_s,
                  sum=>u17_s,
                carry=>u17_c);

u18:csa_1bit port map(
                    a=>u09_c,
                    b=>u010_c,
                    c=>u013_s,
                  sum=>u18_s,
                carry=>u18_c);

--row2
u24:csa_1bit port map(
                    a=>u15_c,
                    b=>u17_s,
                    c=>u18_s,   
                  sum=>u24_s,
                carry=>u24_c);

--row3
u33:csa_1bit port map(
                    a=>u23_c,
                    b=>u24_s,
                    c=>u16_c,   
                  sum=>u3_s(3),
                carry=>u3_c(3));

--------------------------------------
--generate part
--------------------------------------

csa_gen:for i in 0 to 7 generate

first:if(i=0) generate
a0:csa_2weight port map(
       a=>a(8 downto 7),
       b=>b(8 downto 7),
       c=>c(8 downto 7),
       d=>d(7 downto 6),
       e=>e(6 downto 5),
       f=>f(5 downto 4),
       g=>g(4 downto 3),
       h=>h(3 downto 2),
     
       cin_0=>u011_c,
       cin_1=>u012_c,
       cin_2=>u013_c,
       cin_3=>u17_c, 
       cin_4=>u18_c,
       cin_5=>u24_c, 

       cout_0=>a_cout_0(0),
       cout_1=>a_cout_1(0),
       cout_2=>a_cout_2(0),
       cout_3=>a_cout_3(0),
       cout_4=>a_cout_4(0),
       cout_5=>a_cout_5(0),

       cout_to_cpa=>u3_c(5 downto 4),
       sum_to_cpa=>u3_s(5 downto 4));

end generate;

middle:if(i>0) generate
a1_a6:csa_2weight port map(
       a=>a(2*i+8 downto 2*i+7),
       b=>b(2*i+8 downto 2*i+7),
       c=>c(2*i+8 downto 2*i+7),
       d=>d(2*i+7 downto 2*i+6),
       e=>e(2*i+6 downto 2*i+5),
       f=>f(2*i+5 downto 2*i+4),
       g=>g(2*i+4 downto 2*i+3),
       h=>h(2*i+3 downto 2*i+2),
     
       cin_0=>a_cout_0(i-1),
       cin_1=>a_cout_1(i-1),
       cin_2=>a_cout_2(i-1),
       cin_3=>a_cout_3(i-1), 
       cin_4=>a_cout_4(i-1),
       cin_5=>a_cout_5(i-1), 

       cout_0=>a_cout_0(i),
       cout_1=>a_cout_1(i),
       cout_2=>a_cout_2(i),
       cout_3=>a_cout_3(i),
       cout_4=>a_cout_4(i),
       cout_5=>a_cout_5(i),

       cout_to_cpa=>u3_c(2*i+5 downto 2*i+4),
       sum_to_cpa=>u3_s(2*i+5 downto 2*i+4));
end generate;

end generate;

fianl_gen:csa_1weight_odd port map(
        a=>a(23),
        b=>b(23),
        c=>c(23),
        d=>d(22),
        e=>e(21),
        f=>f(20),
        g=>g(19),
        h=>h(18),
     
        cin_0=>a_cout_0(7),
        cin_1=>a_cout_1(7),
        cin_2=>a_cout_2(7),
        cin_3=>a_cout_3(7), 
        cin_4=>a_cout_4(7),
        cin_5=>a_cout_5(7),  

        cout_0=>final_cout_0,
        cout_1=>final_cout_1,
        cout_2=>final_cout_2,
        cout_3=>final_cout_3,
        cout_4=>final_cout_4,
        cout_5=>final_cout_5,
        cout_6=>u3_c(20),
        sum=>u3_s(20));

--------------------------------------
--Ripple Carry Adder
--------------------------------------


CPA:rca_20bit port map(
          x=>u3_s(20 downto 1),
          y=>u3_c(19 downto 0),
          s=>result(23 downto 4));
---------------------------------------

result(0)<=u00_s;
result(1)<=u10_s;
result(2)<=u20_s;
result(3)<=u3_s(0);
end arch;