tri32.v

A small MIPS R2000 implementation in VHDL

module Tri32(I, OE, O);

  input		[31:0] I;
  input		OE;
  output	[31:0] O;

  // output is set to the input if output enable is asserted, tristated otherwise
	  
  assign O = (OE) ? I : 32'hzzzzzzzz;

endmodule